test: Add uart test

hil-test/Cargo.toml

@@ -12,6 +12,10 @@ test = false
 name    = "gpio"
 harness = false
 
+[[test]]
+name    = "uart"
+harness = false
+
 [[test]]
 name    = "spi_full_duplex"
 harness = false
@@ -25,21 +29,20 @@ semihosting   = "0.1.6"
 
 # HAL package:
 esp-hal = { path = "../esp-hal", features = ["defmt", "eh1"], optional = true }
-esp-backtrace = { version = "0.11.0", features = ["exception-handler", "panic-handler", "defmt"], optional = true}
 
 # Traits:
 embedded-hal       = { version = "0.2.7", features = ["unproven"] }
 embedded-hal-async = { version = "1.0.0", optional = true }
 embedded-hal-1     = { version = "1.0.0", package = "embedded-hal" }
 
 [features]
-esp32   = ["esp-hal/esp32", "esp-backtrace/esp32"]
-esp32c2 = ["esp-hal/esp32c2", "esp-backtrace/esp32c2"]
-esp32c3 = ["esp-hal/esp32c3", "esp-backtrace/esp32c3"]
-esp32c6 = ["esp-hal/esp32c6", "esp-backtrace/esp32c6"]
-esp32h2 = ["esp-hal/esp32h2", "esp-backtrace/esp32h2"]
-esp32s2 = ["esp-hal/esp32s2", "esp-backtrace/esp32s2"]
-esp32s3 = ["esp-hal/esp32s3", "esp-backtrace/esp32s3"]
+esp32   = ["esp-hal/esp32"]
+esp32c2 = ["esp-hal/esp32c2"]
+esp32c3 = ["esp-hal/esp32c3"]
+esp32c6 = ["esp-hal/esp32c6"]
+esp32h2 = ["esp-hal/esp32h2"]
+esp32s2 = ["esp-hal/esp32s2"]
+esp32s3 = ["esp-hal/esp32s3"]
 
 # Async & Embassy:
 async = ["dep:embedded-hal-async", "esp-hal?/async"]

hil-test/README.md

@@ -58,7 +58,8 @@ The `hil.yml` workflow will build the test suite for all our available targets a
 
 Currently, here are the Virtual Machines set up for HIL testing:
 - ESP32-C6:
-  - Has an ESP32-C6 connected via USB-JTAG-SERIAL.
+  - Has an `ESP32-C6-DevKitC-1 V1.2` connected via USB-JTAG-SERIAL.
+    - Pins 5 and 6 are connected for `uart` test.
     - Pins 2 and 4 are connected for `spi_full_duplex` test.
   - VM has the following setup:
     ```

hil-test/tests/uart.rs

@@ -0,0 +1,69 @@
+//! UART Test
+//!
+//! Folowing pins are used:
+//! RX    GPIO5
+//! TX    GPIP6
+//!
+//! Connect TX (GPIO6) and RX (GPIO5) pins.
+
+#![no_std]
+#![no_main]
+
+use hil_test::esp_hal::{
+    clock::ClockControl,
+    peripherals::{Peripherals, UART0},
+    prelude::*,
+    timer::TimerGroup,
+    uart::{
+        config::{Config, DataBits, Parity, StopBits},
+        TxRxPins,
+    },
+    Uart, IO,
+};
+use nb::block;
+
+struct Context {
+    uart: Uart<'static, UART0>,
+}
+
+impl Context {
+    pub fn init() -> Self {
+        let peripherals = Peripherals::take();
+        let system = peripherals.SYSTEM.split();
+        let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
+        let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);
+        let pins = TxRxPins::new_tx_rx(
+            io.pins.gpio6.into_push_pull_output(),
+            io.pins.gpio5.into_floating_input(),
+        );
+        let config = Config {
+            baudrate: 115200,
+            data_bits: DataBits::DataBits8,
+            parity: Parity::ParityNone,
+            stop_bits: StopBits::STOP1,
+        };
+
+        let mut uart = Uart::new_with_config(peripherals.UART0, config, Some(pins), &clocks);
+
+        Context { uart }
+    }
+}
+
+#[embedded_test::tests]
+mod tests {
+    use defmt::{assert_eq, unwrap};
+
+    use super::*;
+
+    #[init]
+    fn init() -> Context {
+        Context::init()
+    }
+
+    #[test]
+    fn test_send_receive(mut ctx: Context) {
+        ctx.uart.write(0x42).ok();
+        let read = block!(ctx.uart.read());
+        assert_eq!(read, Ok(0x42));
+    }
+}