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[VSC-1412] Add validation for debug session status for monitor start with no reset flag #1270
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Hi @brianignacio5, PTAL |
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LGTM
Hi @AndriiFilippov PTAL |
Pull request has been marked as |
@radurentea hi ! Tested under: Steps:
Have tried multiple times. Leads to same error. |
Hi @AndriiFilippov, The problem is not related to the change itself, but rather to the debugging process.
However, issues arise when:
In these cases, when we attempt to restart debugging, we encounter errors. I think we can close this issue if the intended behaviour works and open a discussion about the debugging process with @brianignacio5 and @kolipakakondal maybe they have a better understanding if we should and if we can support the a fix for what you found. |
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Confirmed the message is only printed once not in the output.
Tested on Windows and Linux.
Description
JIRA: https://jira.espressif.com:8443/browse/VSC-1412
Type of change
Steps to test this pull request
The board should not reset itself, monitor should start from the current state of the board
How has this been tested?
As described above using the blink example on a ESP32-C6 board
Test Configuration:
Checklist