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FireSim Vs AWS Upstream Tracking #50

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davidbiancolin wants to merge 185 commits intoaws-masterfiresim/aws-fpga-firesim:aws-masterfrom bump-vivado-2021firesim/aws-fpga-firesim:bump-vivado-2021Copy head branch name to clipboard

+1,405,964-12

Commits

Commits on Jun 21, 2017

• start firesim f1 project from prepare_new_cl.sh

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• start from hello world since it\'s closer to what we want

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• rename hello_world -> firesim

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• WIP connect firesim/midas to f1 top

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• check in empty F1Shim, this at least builds (xsim appears to be crashing with full rocket-chip

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• revert to full rocketchip in cl_firesim_generated.sv

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Commits on Jun 22, 2017

• simulator now builds... xsim doesnt like the stuff inside the ifndef SYNTHESIS blocks

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• solved the crash: xsim can't handle properly, remove them all for now

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• hook up DDR interface. this is just for prototyping, only uses 64 bits of 512 bit IF

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Commits on Jun 23, 2017

• fix the hello world C test

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Commits on Jun 24, 2017

• getting reasonable starting responses from hardcoded tests

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• slow, but working MidasTop-f1 + xsim. communicating over pipes

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Commits on Jun 26, 2017

• fix dr -> ddr

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Commits on Jun 27, 2017

• fix master size, add queues, fix simulation

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• runs hello world in xsim with heavy tweaking

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Commits on Jun 28, 2017

• Pull in changes for upstream v1.2.4 release

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Commits on Jun 29, 2017

• using dramsim works in xsim, now trying fpga

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• fix ddr request size to enable using fpga mem model. works in both xsim and on fpga

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Commits on Jun 30, 2017

• emulated backpressure

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• test for b resp after each write

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• cleanup API between simif and xsim

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Commits on Jul 1, 2017

• speed up software sim

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• add .gitignore in cl_firesim

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Commits on Jul 2, 2017

• bump RTL from ec2-pr branch

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Commits on Jul 3, 2017

• no more blocking writes

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Commits on Jul 4, 2017

• use vivado axi width adapter for 64 bit <-> 512 bit conversion for DDR

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• generate IDs for reads

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• gitignore lib dir

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• add clock converters for axi, not yet instantiated

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• instantiate clock converter on AXI OCL

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Commits on Jul 5, 2017

• runs on the FPGA @ 62 MHz with clock crossings using clock recipe A0

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Commits on Jul 8, 2017

• remove width adapter, this actually works reliably now at 62 MHz

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Commits on Jul 10, 2017

• rtl with UART input now supported by UARTWidget

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Commits on Jul 11, 2017

• save utilization reports during runs

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Commits on Jul 16, 2017

• rtl for new rocket-chip

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• bump rtl

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Commits on Jul 17, 2017

• fixed UART rtl, works on fpga

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Commits on Jul 18, 2017

• bump with new output (only name change)

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• bump to output of scripts

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• simplenic RTL works on fpga

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Commits on Jul 23, 2017

• WIP blockdev

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• bump after hardcoded width cleanup

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Commits on Jul 31, 2017

• Merge branch 'master' of github.com:aws/aws-fpga into 1.3_shell

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• update cl_firesim with shell v1.3.0 changes from cl_hello_world

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• add missing v1.2.5 hotfix updates for cl_firesim

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Commits on Aug 5, 2017

• fix address bit width. looks like it runs perlbench now

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Commits on Aug 15, 2017

• boots linux at 90 MHz. see notes:

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Commits on Aug 16, 2017

• default to TIMING strategy

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Commits on Aug 17, 2017

• run shim at 250 MHz, default to clock recipe A1

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Commits on Aug 28, 2017

• run xsim again

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Commits on Sep 10, 2017

• Merge pull request #1 from firesim/fix-xsim

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• Merge branch 'master' of github.com:aws/aws-fpga

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Commits on Sep 12, 2017

• WIP RTL for new RC bump/move to firechip

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• fix gitignore

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• works on FPGA, including NIC

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• bump to 85 MHz clock. 90 failed timing barely (but seems to work in practice)

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Commits on Sep 13, 2017

• bump with endpoint updates to set mac from host

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Commits on Sep 14, 2017

• bump to latest RTL

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Commits on Sep 24, 2017

• working single-core rtl post mem-model-merge (not yet on firesim master)

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Commits on Sep 25, 2017

• Update to upstream aws-fpga 1.3.3. Merge remote-tracking branch 'upstream/master'

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• singlenode rtl for latest built version, should be equivalent to the last one (see firesim/scripts/verilog_equivalence.py)

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Commits on Oct 2, 2017

• Update RTL to match that which would be generated by non-det midas

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Commits on Oct 3, 2017

• Update README.md

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Commits on Oct 5, 2017

• fix endpoint not driving keep field

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Commits on Oct 6, 2017

• bump to removed target io hacks

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Commits on Oct 12, 2017

• expose registers in F1Shim to DMA_PCIS interface directly

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• add sanity check that PCIS is connected properly at top level. requires some changes to common/verif/include/sh_dpi_tasks.svh that are not included

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• both regular firesim linux boot and edma talking to registers works on FPGA

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• bump to RTL with PCIS pushed into SimpleNICWidget

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Commits on Oct 13, 2017

• bump to RTL with Queues attached to PCIS in SimpleNICWidget instead of regs

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Commits on Oct 14, 2017

• queues attached to NIC inputs, add valid check MMIO regs

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• add counters on outgoing/incoming queues for batching

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Commits on Oct 15, 2017

• first test RTL for 512nic + cycle accurate endpoint

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Commits on Oct 17, 2017

• increase queue depth, fix counters

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Commits on Oct 18, 2017

• working RTL with 7 64-bit transacts per 512 bit token. also switch to 75 MHz for faster builds

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Commits on Oct 20, 2017

• working cycle-accurate network

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Commits on Oct 22, 2017

• bump rtl

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Commits on Oct 23, 2017

• rocket-chip bumped rtl

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Commits on Oct 24, 2017

• nic fix

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• update gitignore

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• fix UARTWidget div, PeripheryBusKey's frequency

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Commits on Oct 25, 2017

• [rtl] nic with hellaqueue

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Commits on Oct 26, 2017

• Regenerate the clock generator (190, 175, 160), update rtl

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• update rtl with nic, 1.6 GHz, blockdev with >2GB fix

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• default to 160 MHz for firesim, icenic / simplenicwidget fail timing at 190

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Commits on Oct 29, 2017

• single node with uart queue increases, nic queue increases, uart div back to higher output freq

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Commits on Dec 2, 2017

• merge 1.3.4 from upstream. not yet tested

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• start updating cl_firesim internals for 1.3.4, excluding verif directory so far. also untested

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• propagate remaining 1.3.4 changes into verif

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• fix strategy timing, broke again in upstream

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• bump rtl

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Commits on Dec 3, 2017

• fix XSim build (won't run yet, needs DMA_PCIS)

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Commits on Dec 9, 2017

• Merge branch 'master' of github.com:aws/aws-fpga

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• merge upstream patches to 1.3.4

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• Support 16GiB target memory systems

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Commits on Dec 10, 2017

• Revert "Support 16GiB target memory systems"

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Commits on Jan 29, 2018

• no more generated files

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• no more hacks

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• Merge branch 'master' of github.com:firesim/aws-fpga-firesim into donggyu-bump

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Commits on Feb 8, 2018

• Move simulation defines into makefrags

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Commits on Feb 15, 2018

• Merge pull request #3 from firesim/donggyu-bump-with-mem-model

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• Support 16GiB target memory systems

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Commits on Mar 10, 2018

• reconnect NIC signals

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Commits on Mar 17, 2018

• one clock gen with both sets of clocks that we frequently use (190, 175, 160), (90, 85, 75)

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Commits on Mar 20, 2018

• xdc adds RAM_STYLE ULTRA property. currently hardcoded path

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Commits on Apr 12, 2018

• Fix transaction packing in width adapter

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Commits on Apr 13, 2018

• Fix comments made when i should have been sleeping

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Commits on Apr 18, 2018

• Merge remote-tracking branch 'upstream/master' into width-adapter-fix-upstream-1.3.6

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• apply changes from upstream cl_ example projects to cl_firesim. also eliminate simulators that we dont use, so we dont have to maintain their scripts

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• fix TIMING strategy again

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Commits on Apr 19, 2018

• default to 90MHz, since this is what designs with NIC and/or L2 require

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• add a .gitignore for cl_FireSim*

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Commits on Jul 21, 2018

• Merge tag 'v1.3.8' into bump-aws-fpga-1.3.8

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• pull in changes from cl_dram_dma to cl_firesim for v1.3.8 bump

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• Merge tag 'v1.4.0' into bump-aws-fpga-1.4.0

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• pull in changes from cl_dram_dma to cl_firesim for v1.4.0 bump

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Commits on Jul 22, 2018

• fix constraint that broke during the upgrade

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• cleanup git status. add ddr4_rank.sv from shell download and ignore awsver.txt

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Commits on Jul 29, 2018

• fix xsim simulation (probably not vcs)

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Commits on Jul 30, 2018

• fix vcs FPGA-level simulation

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Commits on Aug 6, 2018

• Prune an unnecessary timing constraint

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• Add false paths to remove recovery failures to reset synchronizers

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Commits on Aug 8, 2018

• Merge pull request #7 from firesim/cut-paths

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Commits on Aug 11, 2018

• tie off/attach new ddr/pcis signals

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• fix .gitignore for FireBOOM

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Commits on Aug 12, 2018

• Merge pull request #8 from firesim/connect-new-signals

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• Update README.md

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• Merge pull request #10 from firesim/fix-readme

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Commits on Aug 13, 2018

• Merge pull request #9 from firesim/dev

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Commits on Sep 7, 2018

• auto-ila base

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Commits on Sep 20, 2018

• Merge pull request #11 from firesim/auto-ila

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Commits on Sep 22, 2018

• Merge pull request #12 from firesim/dev

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Commits on Nov 4, 2018

• add DDR channels

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Commits on Nov 8, 2018

• fix synthesis script

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Commits on Nov 28, 2018

• uram contraint

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• add stuff to xsim makefiles

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• fix typo in cl_firesim.sv

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Commits on Nov 29, 2018

• remove redundant include for xsim

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• select frequency from included header

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• missing file copy in encrypt.tcl

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• vivado didn't like previous style of macro, had to switch to something

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Commits on Nov 30, 2018

• Merge pull request #13 from firesim/firesim-supernode-integration

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Commits on Dec 6, 2018

• more constraints

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Commits on Dec 9, 2018

• Merge pull request #15 from firesim/more-supernode

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Commits on Dec 14, 2018

• Add a wildcard to URAM inference constraint

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• Merge pull request #16 from firesim/uram-wildcard

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Commits on Jan 25, 2019

• Merge remote-tracking branch 'upstream/master' into aws-fpga-upstream-1.4.6

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• update cl_firesim with changes required by upstream aws-fpga 1.4.6

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Commits on Feb 1, 2019

• fix xsim

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• Merge pull request #17 from firesim/aws-fpga-upstream-1.4.6

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Commits on Feb 25, 2019

• Merge pull request #18 from firesim/dev

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Commits on Apr 16, 2019

• Merge remote-tracking branch 'upstream/master' into aws-fpga-upstream-1.4.8

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Commits on Apr 17, 2019

• update gitignore

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Commits on Apr 19, 2019

• Merge pull request #19 from firesim/aws-fpga-upstream-1.4.8

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Commits on Apr 23, 2019

• Generate PLL IP on every build with a single desired frequency

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• Fix FPGA-Level Simulation (#24)

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Commits on Apr 7, 2020

• Remove unneeded connections between DRAM and F1Shim

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Commits on May 31, 2020

• Merge pull request #25 from firesim/dev

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• Promote design partially routed and timing failures to fatal errors

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• Sort paths by slack; and check hold-timing slack

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Commits on Jan 26, 2021

• Error out on partially routed clock nets

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• Merge pull request #29 from firesim/dev

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• Merge pull request #31 from firesim/clock-net-failures

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Commits on Feb 25, 2021

• Add strategy to remove -retime flag from Vivado

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• Merge pull request #34 from firesim/no-retiming

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• Finish adding support for NORETIMING strategy

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• Merge pull request #35 from firesim/no-retiming

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• Merge tag 'v1.4.18' into dev

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Commits on Apr 7, 2021

• Suppress same messages as the dma_dram example

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Commits on Apr 9, 2021

• Report clock utilization

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• Merge remote-tracking branch 'upstream/master' into aws-1.4.18-bump

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• add more reports (#37)

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Commits on Jun 10, 2021

• Demote Route 35-1 back to CW

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• Merge pull request #32 from firesim/dev

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• Workaround clock-partitioning error by disabling phys opt

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• Merge remote-tracking branch 'origin/master' into aws-1.4.18-bump

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Commits on Jun 15, 2021

• Re-enable post-placement phys_opt

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• Merge pull request #39 from firesim/vivado-2020-bump2

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Commits on Jun 21, 2021

• Add dont_touch to all dummy clock loads

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• Import basic floorplan from cl_dram_dma

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• Merge pull request #40 from firesim/clock-partitioning

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Commits on Jul 27, 2021

• Update filenames to reflect new output file strategy.

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• Merge pull request #42 from firesim/file-emission

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• Selective instantiate DRAM controllers + CDC + Width apaters

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• Merge remote-tracking branch 'upstream/master' into HEAD

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