Z80 code generated decoder structure rework. (#106)

.gitignore

@@ -1,4 +1,6 @@
 .vscode/
+.venv/
+__pycache__/
 #>fips
 # this area is managed by fips, do not edit
 .fips-*

CHANGELOG.md

@@ -1,5 +1,19 @@
 ## What's New
 
+* **02-Jan-2024**: Integrated some 'structural ideas' from the Zig Z80 emulator into z80.h
+  (everything backward compatible and no behaviour changes):
+  - Got rid of lookup tables which mapped opcodes to the first instruction
+    payload step in the decoder switch-case statement. Instead the first
+    512 case-branches in the decoder switch-case directly map to the first
+    (and for 4-cycle instructions: only) payload step (256 for the main
+    instruction subset and the next 256 for the ED-prefixed subset).
+  - Stepping to the next decoder step is now always 'exclusive', instead
+    of incrementing the current step, an explicit step number is written.
+    This appears to be a tiny faster.
+  - The separate input template files for the code generation of the Z80
+    and M6502 emulators have been removed, instead the generated code is
+    now injected into the actual source files (search for `<%` and `%>` markers).
+
 * **24-Dec-2024**: complete UI overhaul:
 
   - switched to the Dear ImGui docking branch

chips/m6502.h

@@ -768,6 +768,7 @@ uint64_t m6502_tick(m6502_t* c, uint64_t pins) {
     // reads are default, writes are special
     _RD();
     switch (c->IR++) {
+    // <% decoder
     /* BRK  */
         case (0x00<<3)|0: _SA(c->PC);break;
         case (0x00<<3)|1: if(0==(c->brk_flags&(M6502_BRK_IRQ|M6502_BRK_NMI))){c->PC++;}_SAD(0x0100|c->S--,c->PC>>8);if(0==(c->brk_flags&M6502_BRK_RESET)){_WR();}break;
@@ -3072,7 +3073,7 @@ uint64_t m6502_tick(m6502_t* c, uint64_t pins) {
         case (0xFF<<3)|5: c->AD++;_SD(c->AD);_m6502_sbc(c,c->AD);_WR();break;
         case (0xFF<<3)|6: _FETCH();break;
         case (0xFF<<3)|7: assert(false);break;
-
+    // %>
     }
     M6510_SET_PORT(pins, c->io_pins);
     c->PINS = pins;