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honor the 'ready' signal from the GCD output #153

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honor the 'ready' signal from the GCD output #153

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4f5783d
honor the 'ready' signal from the GCD output
wunderabt May 17, 2021
030bd81
use a 8to1 clock divider to force some backpressure but it elaborates…
wunderabt May 19, 2021
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36 changes: 23 additions & 13 deletions 2.6_chiseltest.ipynb
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Original file line number Diff line number Diff line change
Expand Up @@ -420,26 +420,26 @@
" val x = Reg(UInt())\n",
" val y = Reg(UInt())\n",
" val busy = RegInit(false.B)\n",
" val resultValid = RegInit(false.B)\n",
"\n",
" input.ready := ! busy\n",
" output.valid := resultValid\n",
" output.bits := DontCare\n",
" output.valid := false.B\n",
"\n",
" when(busy) {\n",
" // during computation keep subtracting the smaller from the larger\n",
" when(x > y) {\n",
" x := x - y\n",
" when(y > 0.U) {\n",
" when(x > y) {\n",
" x := x - y\n",
" }.otherwise {\n",
" y := y - x\n",
" }\n",
" }.otherwise {\n",
" y := y - x\n",
" }\n",
" when(y === 0.U) {\n",
" // when y becomes zero computation is over, signal valid data to output\n",
" output.bits.value1 := xInitial\n",
" output.bits.value2 := yInitial\n",
" output.bits.gcd := x\n",
" output.valid := true.B\n",
" busy := false.B\n",
" busy := ! output.ready\n",
" }\n",
" }.otherwise {\n",
" when(input.valid) {\n",
Expand All @@ -450,7 +450,7 @@
" xInitial := bundle.value1\n",
" yInitial := bundle.value2\n",
" busy := true.B\n",
" resultValid := false.B\n",
" output.valid := false.B\n",
" }\n",
" }\n",
"}\n"
Expand Down Expand Up @@ -483,9 +483,19 @@
"metadata": {},
"outputs": [],
"source": [
"test(new DecoupledGcd(16)) { dut =>\n",
"\n",
"test(new MultiIOModule {\n",
" val input = IO(Flipped(Decoupled(new GcdInputBundle(16))))\n",
" val output = IO(Decoupled(new GcdOutputBundle(16)))\n",
" val clk8to1 = IO(Output(Clock()))\n",
" val gcd = Module(new DecoupledGcd(16))\n",
" gcd.input := input\n",
" output := gcd.output\n",
" val cnt = Counter(true.B, 16)\n",
" clk8to1 := cnt._1(3).asClock\n",
"}) { dut =>\n",
" dut.input.initSource().setSourceClock(dut.clock)\n",
" dut.output.initSink().setSinkClock(dut.clock)\n",
" dut.output.initSink().setSinkClock(dut.clk8to1) // the sink uses a slower clock so that backpressure is more likely\n",
"\n",
" val testValues = for { x <- 1 to 10; y <- 1 to 10} yield (x, y)\n",
" val inputSeq = testValues.map { case (x, y) =>\n",
Expand All @@ -500,7 +510,7 @@
" }.fork {\n",
" dut.output.expectDequeueSeq(resultSeq)\n",
" }.join()\n",
"}\n"
"}"
]
},
{
Expand Down Expand Up @@ -531,4 +541,4 @@
},
"nbformat": 4,
"nbformat_minor": 2
}
}