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core: riscv: Use sp as base register of load instructions #594

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core: riscv: Use sp as base register of load instructions

core: riscv: Use sp as base register of load instructions #594

Triggered via push September 16, 2024 08:52
@gagachanggagachang
pushed 6f750c6
dev-riscv-improve-0913
Status Success
Total duration 43m 34s
Artifacts –

ci.yml

on: push
Code style
49s
Code style
make (multi-platform)
43m 23s
make (multi-platform)
make check (QEMUv7)
34m 17s
make check (QEMUv7)
make check (QEMUv8)
40m 47s
make check (QEMUv8)
make check (QEMUv8, Xen)
25m 6s
make check (QEMUv8, Xen)
make check (QEMUv8, Xen FF-A)
25m 4s
make check (QEMUv8, Xen FF-A)
make check (QEMUv8, Hafnium)
21m 30s
make check (QEMUv8, Hafnium)
make check (QEMUv8, BTI+MTE+PAC)
18m 41s
make check (QEMUv8, BTI+MTE+PAC)
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