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core: riscv: Use sp as base register of load instructions #595

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core: riscv: Use sp as base register of load instructions

core: riscv: Use sp as base register of load instructions #595

Run time

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Job Run time
Code style
50s
make check (QEMUv8)
38m 43s
make check (QEMUv7)
32m 28s
make (multi-platform)
22m 13s
make check (QEMUv8, Xen)
23m 46s
make check (QEMUv8, Xen FF-A)
24m 41s
make check (QEMUv8, BTI+MTE+PAC)
17m 36s
make check (QEMUv8, Hafnium)
20m 53s
3h 1m 10s