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core: riscv: Support Privileged Access Never by CSR status.SUM bit #225

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core: riscv: Support Privileged Access Never by CSR status.SUM bit

core: riscv: Support Privileged Access Never by CSR status.SUM bit #225

Triggered via push August 30, 2023 09:08
@gagachanggagachang
pushed 8d2ddab
dev-riscv-pan
Status Failure
Total duration 1h 25m 52s
Artifacts –

ci.yml

on: push
Code style
2m 1s
Code style
make (multi-platform)
12m 56s
make (multi-platform)
make check (QEMUv8)
30m 9s
make check (QEMUv8)
make check (QEMUv8, Xen)
1h 25m
make check (QEMUv8, Xen)
make check (QEMUv8, BTI+MTE+PAC)
28m 8s
make check (QEMUv8, BTI+MTE+PAC)
make check-rust (QEMUv8)
27m 59s
make check-rust (QEMUv8)
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1 error
make (multi-platform)
Process completed with exit code 2.