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core: riscv: Disable traps by clearing XIE CSR
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Ensure we disable traps by clearing XIE CSR instead of clearing
XSTATUS.IE which is global interrupt enable bit.

Signed-off-by: Alvin Chang <[email protected]>
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@gagachang
gagachang committed Oct 14, 2024
1 parent 136cc65 commit 17802aa
Showing 1 changed file with 2 additions and 2 deletions.
4 changes: 2 additions & 2 deletions core/arch/riscv/kernel/thread_optee_abi_rv.S
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Expand Up @@ -46,8 +46,8 @@ FUNC thread_std_abi_entry , :
/* Save return value */
mv s0, a0

/* Disable all interrupts */
csrc CSR_XSTATUS, CSR_XSTATUS_IE
/* Mask all maskable exceptions before switching to temporary stack */
csrw CSR_XIE, x0

/* Switch to temporary stack */
jal thread_get_tmp_sp
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@lyctw lyctw commented on 17802aa Oct 14, 2024

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Reviewed-by: Yu Chien Peter Lin <[email protected]>

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