core: riscv: Disable traps by clearing XIE CSR

Ensure we disable traps by clearing XIE CSR instead of clearing XSTATUS.IE which is global interrupt enable bit. Signed-off-by: Alvin Chang <[email protected]> Reviewed-by: Yu Chien Peter Lin <[email protected]> Reviewed-by: Marouene Boubakri <[email protected]>
gagachang · Nov 4, 2024 · 3b5e85c · 3b5e85c
1 parent 75be62a
commit 3b5e85c
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/core/arch/riscv/kernel/thread_optee_abi_rv.S b/core/arch/riscv/kernel/thread_optee_abi_rv.S
@@ -46,8 +46,8 @@ FUNC thread_std_abi_entry , :
 	/* Save return value */
 	mv	s0, a0
 
-	/* Disable all interrupts */
-	csrc	CSR_XSTATUS, CSR_XSTATUS_IE
+	/* Mask all maskable exceptions before switching to temporary stack */
+	csrw	CSR_XIE, x0
 
 	/* Switch to temporary stack */
 	jal	thread_get_tmp_sp