riscv: virt: Enable configurations for S-mode execution

In RISC-V QEMU virtual platform, we run OP-TEE as S-mode. This commit forcely enables CFG_RISCV_S_MODE and disables CFG_RISCV_M_MODE. Also, we enable CFG_RISCV_SBI so that OP-TEE utilizes SBI to communicate with other OS. Signed-off-by: Alvin Chang <[email protected]> Acked-by: Jerome Forissier <[email protected]> Reviewed-by: Marouene Boubakri <[email protected]>
gagachang · Dec 7, 2023 · 6004e80 · 6004e80
1 parent 76438b8
commit 6004e80
Showing 1 changed file with 3 additions and 0 deletions.
diff --git a/core/arch/riscv/plat-virt/conf.mk b/core/arch/riscv/plat-virt/conf.mk
@@ -20,11 +20,14 @@ $(call force,CFG_BOOT_SYNC_CPU,y)
 # RISC-V-specific flags
 rv64-platform-isa ?= rv64imafdc_zicsr_zifencei
 
+$(call force,CFG_RISCV_M_MODE,n)
+$(call force,CFG_RISCV_S_MODE,y)
 $(call force,CFG_RISCV_PLIC,y)
 $(call force,CFG_SBI_CONSOLE,n)
 $(call force,CFG_16550_UART,y)
 $(call force,CFG_RISCV_TIME_SOURCE_RDTIME,y)
 CFG_RISCV_MTIME_RATE ?= 10000000
+CFG_RISCV_SBI ?= y
 
 # TA-related flags
 supported-ta-targets = ta_rv64