core: change get_core_pos_mpidr() to support hypervisor

The secure hypervisor, such as Hafnium, is expected to manipulate MPIDR_EL1 to indicate a VCPU ID. This commit makes get_core_pos_mpidr() not calculate a CPU ID using the affinity bitfields of MPIDR_EL1 when there is a hypervisor in SEL2. Reviewed-by: Jens Wiklander <[email protected]> Acked-by: Etienne Carriere <[email protected]> Signed-off-by: Sungbae Yoo <[email protected]>
gagachang · Nov 12, 2024 · f0489ba · f0489ba
1 parent dd7b51e
commit f0489ba
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diff --git a/core/arch/arm/include/arm.h b/core/arch/arm/include/arm.h
@@ -76,6 +76,9 @@
 #define MPIDR_AARCH32_AFF_MASK	(MPIDR_AFF0_MASK | MPIDR_AFF1_MASK | \
 				 MPIDR_AFF2_MASK)
 
+/* MPIDR definitions for VCPU */
+#define MPIDR_VCPU_MASK		ULL(0xffffff)
+
 /* ID_ISAR5 Cryptography Extension masks */
 #define ID_ISAR5_AES		GENMASK_32(7, 4)
 #define ID_ISAR5_SHA1		GENMASK_32(11, 8)

diff --git a/core/arch/arm/kernel/misc_a64.S b/core/arch/arm/kernel/misc_a64.S
@@ -17,6 +17,10 @@ END_FUNC __get_core_pos
 /* size_t get_core_pos_mpidr(uint32_t mpidr); */
 /* Let platforms override this if needed */
 WEAK_FUNC get_core_pos_mpidr , :
+#if CFG_CORE_SEL2_SPMC
+	mov	x1, #MPIDR_VCPU_MASK
+	and	x0, x0, x1
+#else /* CFG_CORE_SEL2_SPMC */
 	/*
 	 * Shift MPIDR value if it's not already shifted.
 	 * Using logical shift ensures AFF0 to be filled with zeroes.
@@ -47,6 +51,7 @@ WEAK_FUNC get_core_pos_mpidr , :
 	ubfx	x2, x3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
 	add	x1, x1, x2, LSL #(CFG_CORE_CLUSTER_SHIFT)
 	add	x0, x0, x1, LSL #(CFG_CORE_THREAD_SHIFT)
+#endif
 #endif
 
 	ret