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DEMO: Inverter schematic-driven-layout using gplugins + possible SPICE simulations #86
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I believe the ideal interim solution in relation to https://github.com/efabless/sky130_klayout_pdk would be to have the fixed as a submodule and gdsfactory recursing though them to get the cell declarations. Ultimately, this is an application repository that builds onto the existing pdks. As such, and given that most users are using |
Hey @joamatab just to keep you posted: I've managed to fix things to get schematic-driven-layout from the sky130nm PDK using the gplugins schematic editor. However, there's a serious dependency hell I had to sort out, and when I've got it reproducible enough in the sky130nm repo, I'll migrate the examples there which I'm currently working on between multiple repos atm. Think I have a plan to automate going from hdl21 models to the yaml too. The next few weeks I'll be broadly working on the stuff for the conference fyi. The next step after that is going from an xschem SPICE declaration into some python construct using vlsir, but it's a bit more involved. I'm trying to avoid writing a spice parser as there are so many variations to reconstruct the parameters. |
Just thought to make this issue to break down the tasks and get my head around the latest updates:
We have the skywater PDK currently, and want to integrate a more standard schematic-to-layout flow using gdsfactory
Would the goal be to export a SPICE netlist from a given schematic-capture tool eg. and then performing the layout accordingly using the gdsfactory layout generator?
Caveats to consider:
Requirements:
So we would need to generate the first set of spice desciptions, convert to yaml, and then integrate the layout flow. I assume the idea of using "jupyter notebooks, QUCs and XSchem" would be to automate this generation.
The tasks then become:
So the place to start would be explore the current schematic representation or design flow as currently implemented? Make sure the names match, or a interface interconnection is explicit, in order to then make sure that the sky130nm PCells can be related to the schematic description. Test the SPICE conversion accordingly, make sure the layout can be fundamentally generated using this PDK and go from there.
Existing resources in this direction:
Thoughts:
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