Conv 2D CPU Implementation #352
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Contributor
dmille
commented
Jul 7, 2023
•
dmille
commented
- Variable padding (p0 and p1)
- Variable stride (s0 and s1)
- Variable dilation (d0 and d1)
- f16 kernel, f32 input tensor
- Utilizes ggml_vec_dot_f16 (SIMD optimized)
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Thanks! Let's resolve the conflicts and merge |
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@ggerganov Conflicts are resolved! |
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Thanks! Will first look to merge #325 and then this one |
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I needed strides of variable length for my project so I went ahead and updated the function to support both dilation and strides. |
ggerganov
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Jul 14, 2023
CCLDArjun
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Dec 18, 2023
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