Add a shim header to support locking without ldrex/strex

[martinling]

Required to allow the USB queue code to be built for the M0.

[u-foka]

Required to allow the USB queue code to be built for the M0.

Hello again :) Sorry to bug you with this, but to achieve this goal, it would be great if you could also change the nvic.h include to dispatch ;) Thanks for all the help!

#1516 (comment)

[miek]

One minor concern I have is about the side-effects of using one of the functions on their own (and leaving interrupts disabled for example) but, given that ldrex/strex must be used in a pair, I'm ok with assuming that for these functions too. I think it'd be worth adding a comment to that effect though.

[martinling]

Both changes made.

[gullradriel]

Thanks a lot :-)

[gullradriel]

Back from testing.
Sorry for pinging you anew, @martinling .
Compiling on M0 is giving errors for undefined references to the intrinsic __disable_irq and __enable_irq.
The only two solutions for us were to either #include "hal.h" from chibios, or use the asm alternatives to those functions.
Since I don't think hackrf code is using chibios, would it be possible to use the following code instead:

static inline uint32_t load_exclusive(volatile uint32_t* addr)
{
    __asm volatile ("cpsid i");  // __disable_irq();
    return *addr;
}

static inline uint32_t store_exclusive(uint32_t val, volatile uint32_t* addr)
{
    *addr = val;
    __asm volatile ("cpsie i");  // __enable_irq();
    return 0;
}

Or maybe you prefer the version with the "memory" clobber ?

static inline uint32_t load_exclusive(volatile uint32_t* addr)
{
    __asm volatile ("cpsid i" ::: "memory");  // __disable_irq();
    return *addr;
}

static inline uint32_t store_exclusive(uint32_t val, volatile uint32_t* addr)
{
    *addr = val;
    __asm volatile ("cpsie i" ::: "memory");  // __enable_irq();
    return 0;
}