Merge branch 'abadams/fix_riscv_vx_vi' into abadams/fix_7871

halide · Oct 4, 2023 · b2e3cc3 · b2e3cc3
2 parents 568573e + 33fa8a6
commit b2e3cc3
Showing 1 changed file with 8 additions and 4 deletions.
diff --git a/test/correctness/simd_op_check_riscv.cpp b/test/correctness/simd_op_check_riscv.cpp
@@ -70,10 +70,14 @@ class SimdOpCheckRISCV : public SimdOpCheckTest {
         // Basic math operations.
         check("vadd.vv", lanes, i_1 + i_2);
         check("vadd.vv", lanes, u_1 + u_2);
-        check("vadd.vi", lanes, i_1 + 2);
-        check("vadd.vi", lanes, u_1 + 2);
-        check("vadd.vx", lanes, i_1 + 42);
-        check("vadd.vx", lanes, u_1 + 42);
+
+        // Vector + immediate / scalar form. Disabled because LLVM 18 broadcasts
+        // scalars to vectors registers outside the loop.
+        // check("vadd.vi", lanes, i_1 + 2);
+        // check("vadd.vi", lanes, u_1 + 2);
+        // check("vadd.vx", lanes, i_1 + 42);
+        // check("vadd.vx", lanes, u_1 + 42);
+
         check("vsub.vv", lanes, i_1 - i_2);
         check("vsub.vv", lanes, u_1 - u_2);
         // TODO: these seem to compile to a vector add