RT1170 enhancements

[HiFiPhile]

Describe the PR

• Replace cache clean/invalidate by MPU config. Since we can't guarantee buffer sizes are multiple of cache line size, doing cache clean/invalidate can cause data consistency issue, it also hurts performance. Use MPU to set RAM as non-cacheable like mcux-sdk example.
• Add M4 core ram image build support
  • cmake -DCMAKE_BUILD_TYPE=RelWithDebInfo -DBOARD=mimxrt1170_evkb -DM4=1 -G Ninja -B rt1170_cm4
  • make BOARD=mimxrt1170_evkb M4=1

PS: MCHP has nice write-up on cache https://ww1.microchip.com/downloads/en/DeviceDoc/Managing-Cache-Coherency-on-Cortex-M7-Based-MCUs-DS90003195A.pdf

[HiFiPhile]

On M7 core NonCacheable is located on DTCM so there is no need to add a if switch.

[HiFiPhile]

Hi @mastupristi,

I've managed to run TinyUSB stack on M4 core. The DMA controller inside USB IP can't access M4 core's TCM so packet buffer must be placed in OCRAM, it's done by CFG_TUSB_MEM_SECTION=__attribute__((section("NonCacheable"))), it is a section defined by default linker script.
Also memory section attribute is configured by BOARD_ConfigMPU();

[mastupristi]

Hi @HiFiPhile

I've managed to run TinyUSB stack on M4 core. The DMA controller inside USB IP can't access M4 core's TCM so packet buffer must be placed in OCRAM, it's done by CFG_TUSB_MEM_SECTION=__attribute__((section("NonCacheable"))), it is a section defined by default linker script. Also memory section attribute is configured by BOARD_ConfigMPU();

Just wanted to share some great news—I ran an initial test (cdc_msc example) of your branch for the CM4 on the RT1170, and it worked like a charm! 🎉

Here what my kernel say:

Thanks so much for putting this together so quickly. We’re thrilled with the progress and super grateful for your help.
My colleagues and I will also try to review the code soon