update vpr and vtr

content/items/vpr.md

@@ -4,10 +4,29 @@ description: Open source academic CAD tool designed for the exploration of new F
 authors: []
 links:
   docs: https://docs.verilogtorouting.org/en/latest/vpr/
-tags: []
+categories: [
+  "Tools",
+  "Tools:PnRs"
+]
+tags: [
+  "packing",
+  "placement",
+  "routing",
+  "FASM",
+]
+active:
+  from: 1997
+licenses: [
+  "MIT"
+]
 talk: 124
 ---
 
-This is a long description...
-<!--more-->
-... about VPR.
+*"VPR (Versatile Place and Route) is an open source academic CAD tool designed for the exploration of new FPGA architectures and CAD algorithms, at the packing, placement and routing phases of the CAD flow \[...\]. Since its public introduction, VPR has been used extensively in many academic projects partly because it is robust, well documented, easy-to-use, and can flexibly target a range of architectures."*
+
+*"VPR takes, as input, a description of an FPGA architecture along with a technology-mapped user circuit. It then performs packing, placement, and routing to map the circuit onto the FPGA. The output of VPR includes the FPGA configuration needed to implement the circuit and statistics about the final mapped design (eg. critical path delay, area, etc)."*
+
+References:
+
+- VPR is part of the [Verilog to Routing]({{< ref "/items/vtr" >}} "Verilog to Routing") project
+- [FASM]({{< ref "/items/fasm" >}} "FASM")

content/items/vtr.md

@@ -1,17 +1,48 @@
 ---
 title: Verilog to Routing (VTR)
-description: Open-source CAD tools for FPGA architecture and CAD research
+description: Open Source CAD Flow for FPGA Research
 authors: []
 links:
   web: https://verilogtorouting.org
   gh: verilog-to-routing/vtr-verilog-to-routing
+categories: [
+  "Frameworks",
+  "Tools",
+  "Tools:PnRs",
+  "Tools:Synthesizers"
+]
 tags: [
   "synthesis",
+  "packing",
+  "placement",
+  "routing",
+  "sta",
   "verilog",
+  "odin",
+  "ABC",
+  "VPR",
+  "FASM",
+]
+active:
+  from: 2011
+licenses: [
+  "MIT"
 ]
 talk: 123
 ---
 
-This is a long description...
-<!--more-->
-... about VTR.
+*"The Verilog-to-Routing (VTR) project is a world-wide collaborative effort to provide a open-source framework for conducting FPGA architecture and CAD research and development. The VTR design flow takes as input a Verilog description of a digital circuit, and a description of the target FPGA architecture."*
+
+It performs:
+* Elaboration & Synthesis (ODIN II)
+* Logic Optimization & Technology Mapping (ABC)
+* Packing, Placement, Routing & Timing Analysis (VPR)
+
+*"to generate FPGA speed and area results. \[...\] VTR can also produce FASM to program some commercial FPGAs (via Symbiflow)."*
+
+References:
+
+- [Yosys]({{< ref "/items/yosys" >}} "Yosys")
+- [Versatile Place and Route]({{< ref "/items/vpr" >}} "Versatile Place and Route")
+- [SymbiFlow]({{< ref "/items/symbiflow" >}} "SymbiFlow")
+- [FASM]({{< ref "/items/fasm" >}} "FASM")