Update of PCI scanning process in fdt

Cargo.toml

@@ -14,6 +14,7 @@ cfg-if = "1"
 hermit-entry = { version = "0.10", features = ["loader"] }
 log = "0.4"
 one-shot-mutex = "0.1"
+pci_types = { version = "0.6" }
 sptr = "0.3"
 take-static = "0.1"
 vm-fdt = { version = "0.3", default-features = false, features = ["alloc"] }
@@ -27,6 +28,7 @@ multiboot = "0.8"
 
 [target.'cfg(target_arch = "x86_64")'.dependencies]
 uart_16550 = "0.3"
+x86 = { version = "0.52", default-features = false }
 x86_64 = { version = "0.15", default-features = false, features = ["instructions"] }
 
 [target.'cfg(target_arch = "aarch64")'.dependencies]

src/arch/x86_64/devicetree.rs

@@ -0,0 +1,36 @@
+use alloc::format;
+use alloc::vec::Vec;
+
+use log::{debug, info};
+use multiboot::information::{MemoryType, Multiboot};
+use pci_types::{Bar, EndpointHeader, PciAddress, PciHeader, MAX_BARS};
+use vm_fdt::{FdtWriter, FdtWriterResult};
+
+use super::multiboot::{mb_info, Mem};
+use super::pci::{PciConfigRegion, PCI_MAX_BUS_NUMBER, PCI_MAX_DEVICE_NUMBER};
+use crate::fdt::Fdt;
+
+pub struct DeviceTree;
+
+impl DeviceTree {
+	pub fn create() -> FdtWriterResult<&'static [u8]> {
+		let mut mem = Mem;
+		let multiboot = unsafe { Multiboot::from_ptr(mb_info as u64, &mut mem).unwrap() };
+
+		let memory_regions = multiboot
+			.memory_regions()
+			.expect("Could not find a memory map in the Multiboot information");
+
+		let mut fdt = Fdt::new("multiboot")?.memory_regions(memory_regions)?;
+
+		if let Some(cmdline) = multiboot.command_line() {
+			fdt = fdt.bootargs(cmdline)?;
+		}
+
+		fdt = fdt.pci()?;
+
+		let fdt = fdt.finish()?;
+
+		Ok(fdt.leak())
+	}
+}

src/arch/x86_64/mod.rs

@@ -9,8 +9,10 @@ cfg_if::cfg_if! {
 }
 
 mod console;
+mod devicetree;
 #[cfg(target_os = "none")]
 mod paging;
+pub(crate) mod pci;
 #[cfg(target_os = "none")]
 mod physicalmem;
 

src/arch/x86_64/multiboot.rs

@@ -14,21 +14,22 @@ use x86_64::structures::paging::{PageSize, PageTableFlags, Size2MiB, Size4KiB};
 
 use super::paging;
 use super::physicalmem::PhysAlloc;
+use crate::arch::x86_64::devicetree::DeviceTree;
 use crate::arch::x86_64::{KERNEL_STACK_SIZE, SERIAL_IO_PORT};
 use crate::fdt::Fdt;
 use crate::BootInfoExt;
 
 extern "C" {
 	static mut loader_end: u8;
-	static mb_info: usize;
+	pub(crate) static mb_info: usize;
 }
 
 #[allow(bad_asm_style)]
 mod entry {
 	core::arch::global_asm!(include_str!("entry.s"));
 }
 
-struct Mem;
+pub(crate) struct Mem;
 
 impl MemoryManagement for Mem {
 	unsafe fn paddr_to_slice<'a>(&self, p: PAddr, sz: usize) -> Option<&'static [u8]> {
@@ -48,29 +49,6 @@ impl MemoryManagement for Mem {
 	}
 }
 
-pub struct DeviceTree;
-
-impl DeviceTree {
-	pub fn create() -> FdtWriterResult<&'static [u8]> {
-		let mut mem = Mem;
-		let multiboot = unsafe { Multiboot::from_ptr(mb_info as u64, &mut mem).unwrap() };
-
-		let memory_regions = multiboot
-			.memory_regions()
-			.expect("Could not find a memory map in the Multiboot information");
-
-		let mut fdt = Fdt::new("multiboot")?.memory_regions(memory_regions)?;
-
-		if let Some(cmdline) = multiboot.command_line() {
-			fdt = fdt.bootargs(cmdline)?;
-		}
-
-		let fdt = fdt.finish()?;
-
-		Ok(fdt.leak())
-	}
-}
-
 pub fn find_kernel() -> &'static [u8] {
 	use core::cmp;
 

src/arch/x86_64/pci.rs

@@ -0,0 +1,50 @@
+use pci_types::{ConfigRegionAccess, PciAddress};
+use x86::io::*;
+
+pub(crate) const PCI_MAX_BUS_NUMBER: u8 = 32;
+pub(crate) const PCI_MAX_DEVICE_NUMBER: u8 = 32;
+
+pub(crate) const PCI_CONFIG_ADDRESS_PORT: u16 = 0xCF8;
+const PCI_CONFIG_ADDRESS_ENABLE: u32 = 1 << 31;
+
+const PCI_CONFIG_DATA_PORT: u16 = 0xCFC;
+
+#[derive(Debug, Copy, Clone)]
+pub(crate) struct PciConfigRegion;
+
+impl PciConfigRegion {
+	pub const fn new() -> Self {
+		Self {}
+	}
+}
+
+impl ConfigRegionAccess for PciConfigRegion {
+	#[inline]
+	fn function_exists(&self, _address: PciAddress) -> bool {
+		true
+	}
+
+	#[inline]
+	unsafe fn read(&self, pci_addr: PciAddress, register: u16) -> u32 {
+		let address = PCI_CONFIG_ADDRESS_ENABLE
+			| u32::from(pci_addr.bus()) << 16
+			| u32::from(pci_addr.device()) << 11
+			| u32::from(register);
+		unsafe {
+			outl(PCI_CONFIG_ADDRESS_PORT, address);
+			u32::from_le(inl(PCI_CONFIG_DATA_PORT))
+		}
+	}
+
+	#[inline]
+	unsafe fn write(&self, pci_addr: PciAddress, register: u16, value: u32) {
+		let address = PCI_CONFIG_ADDRESS_ENABLE
+			| u32::from(pci_addr.bus()) << 16
+			| u32::from(pci_addr.device()) << 11
+			| u32::from(register);
+		unsafe {
+			outl(PCI_CONFIG_ADDRESS_PORT, address);
+			outl(PCI_CONFIG_DATA_PORT, value.to_le());
+		}
+	}
+}