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New snippets for Verilog and some reorganization #1522

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New snippets for Verilog and some reorganization #1522

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Commits on Aug 13, 2024

  1. Organize snippets in alphabetical order according to their names

    @mpkopec
    mpkopec committed Aug 13, 2024
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  2. Add mkopec's Verilog/SystemVerilog snippets

    @mpkopec
    mpkopec committed Aug 13, 2024
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  3. Add descriptions to snippets, remove comments

    @mpkopec
    mpkopec committed Aug 13, 2024
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  4. Reorganize systemverilog snippets to alphabetical order

    @mpkopec
    mpkopec committed Aug 13, 2024
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  5. Change the ${0} to ${n}, to make it possible to leave the snippet after 

    finishing the editing process
    @mpkopec
    mpkopec committed Aug 13, 2024
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  6. Fix the posedge/negedge behaviour adding an empty line after

    @mpkopec
    mpkopec committed Aug 13, 2024
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  7. Add VISUAL to verilog snippets wherever possible

    @mpkopec
    mpkopec committed Aug 13, 2024
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Commits on Aug 14, 2024

  1. Remove whitespace after the snipmate-style snippets to avoid inserting 

    them during expansion.
    @mpkopec
    mpkopec committed Aug 14, 2024
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  2. Add instantiation snippets

    @mpkopec
    mpkopec committed Aug 14, 2024
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Commits on Aug 15, 2024

  1. Add conditional operator

    @mpkopec
    mpkopec committed Aug 15, 2024
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  2. Fix VISUAL in begin-end snippet

    @mpkopec
    mpkopec committed Aug 15, 2024
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Commits on Aug 27, 2024

  1. Add IO snippet for instantiation

    @mpkopec
    mpkopec committed Aug 27, 2024
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