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Add support for Z80 CB table.
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@ibara
ibara committed Apr 4, 2021
1 parent d704790 commit dac1c0d
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3 changes: 2 additions & 1 deletion README.md
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Original file line number Diff line number Diff line change
@@ -1,7 +1,8 @@
d80
===
`d80` is an Intel 8080/Zilog Z80 disassembler.
Supports the entire i80 instruction set and the base Z80 table only (for now).
Supports the entire i80 instruction set and the primary and CB Z80 tables
only (for now).

Usage
-----
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3 changes: 3 additions & 0 deletions source/app.d
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Expand Up @@ -37,6 +37,9 @@ static void disz80(ubyte[] b)
case 0x3a:
writef(insnz80[b[a]].s, b[a + 2], b[a + 1]);
break;
case 0xcb: /// CB table
writef("%s", insnz80cb[b[a + 1]].s);
break;
case 0xd3:
case 0xdb:
writef(insnz80[b[a]].s, b[a + 1]);
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268 changes: 266 additions & 2 deletions source/d80/z80.d
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Expand Up @@ -9,7 +9,7 @@ struct z80 {
}

/**
* Table of base Zilog Z80 instructions.
* Primary table of Zilog Z80 instructions.
*/
z80[] insnz80 = [
{ "nop", 1 },
Expand Down Expand Up @@ -215,7 +215,7 @@ z80[] insnz80 = [
{ "ret\tz", 1 },
{ "ret", 1 },
{ "jp\tz, ", 3 },
{ "xxBITxx", 1 },
{ "xxBITxx", 2 },
{ "call\tz, ", 3 },
{ "call\t", 3 },
{ "adc\ta, ", 2 },
Expand Down Expand Up @@ -269,3 +269,267 @@ z80[] insnz80 = [
{ "cp\t", 2 },
{ "rst\t38h", 1 }
];

/**
* CB table of Z80 instructions.
* n = 0 because all instructions in this table are
* 2 bytes in length and we handle that in the
* primary table.
*/
z80[] insnz80cb = [
{ "rlc\tb", 0 },
{ "rlc\tc", 0 },
{ "rlc\td", 0 },
{ "rlc\te", 0 },
{ "rlc\th", 0 },
{ "rlc\tl", 0 },
{ "rlc\t(hl)", 0 },
{ "rlc\ta", 0 },
{ "rrc\tb", 0 },
{ "rrc\tc", 0 },
{ "rrc\td", 0 },
{ "rrc\te", 0 },
{ "rrc\th", 0 },
{ "rrc\tl", 0 },
{ "rrc\t(hl)", 0 },
{ "rrc\ta", 0 },
{ "rl\tb", 0 },
{ "rl\tc", 0 },
{ "rl\td", 0 },
{ "rl\te", 0 },
{ "rl\th", 0 },
{ "rl\tl", 0 },
{ "rl\t(hl)", 0 },
{ "rl\ta", 0 },
{ "rr\tb", 0 },
{ "rr\tc", 0 },
{ "rr\td", 0 },
{ "rr\te", 0 },
{ "rr\th", 0 },
{ "rr\tl", 0 },
{ "rr\t(hl)", 0 },
{ "rr\ta", 0 },
{ "sla\tb", 0 },
{ "sla\tc", 0 },
{ "sla\td", 0 },
{ "sla\te", 0 },
{ "sla\th", 0 },
{ "sla\tl", 0 },
{ "sla\t(hl)", 0 },
{ "sla\ta", 0 },
{ "sra\tb", 0 },
{ "sra\tc", 0 },
{ "sra\td", 0 },
{ "sra\te", 0 },
{ "sra\th", 0 },
{ "sra\tl", 0 },
{ "sra\t(hl)", 0 },
{ "sra\ta", 0 },
{ "slr\tb", 0 },
{ "slr\tc", 0 },
{ "slr\td", 0 },
{ "slr\te", 0 },
{ "slr\th", 0 },
{ "slr\tl", 0 },
{ "slr\t(hl)", 0 },
{ "slr\ta", 0 },
{ "srr\tb", 0 },
{ "srr\tc", 0 },
{ "srr\td", 0 },
{ "srr\te", 0 },
{ "srr\th", 0 },
{ "srr\tl", 0 },
{ "srr\t(hl)", 0 },
{ "srr\ta", 0 },
{ "bit\t0, b", 0 },
{ "bit\t0, c", 0 },
{ "bit\t0, d", 0 },
{ "bit\t0, e", 0 },
{ "bit\t0, h", 0 },
{ "bit\t0, l", 0 },
{ "bit\t0, (hl)", 0 },
{ "bit\t0, a", 0 },
{ "bit\t1, b", 0 },
{ "bit\t1, c", 0 },
{ "bit\t1, d", 0 },
{ "bit\t1, e", 0 },
{ "bit\t1, h", 0 },
{ "bit\t1, l", 0 },
{ "bit\t1, (hl)", 0 },
{ "bit\t1, a", 0 },
{ "bit\t2, b", 0 },
{ "bit\t2, c", 0 },
{ "bit\t2, d", 0 },
{ "bit\t2, e", 0 },
{ "bit\t2, h", 0 },
{ "bit\t2, l", 0 },
{ "bit\t2, (hl)", 0 },
{ "bit\t2, a", 0 },
{ "bit\t3, b", 0 },
{ "bit\t3, c", 0 },
{ "bit\t3, d", 0 },
{ "bit\t3, e", 0 },
{ "bit\t3, h", 0 },
{ "bit\t3, l", 0 },
{ "bit\t3, (hl)", 0 },
{ "bit\t3, a", 0 },
{ "bit\t4, b", 0 },
{ "bit\t4, c", 0 },
{ "bit\t4, d", 0 },
{ "bit\t4, e", 0 },
{ "bit\t4, h", 0 },
{ "bit\t4, l", 0 },
{ "bit\t4, (hl)", 0 },
{ "bit\t4, a", 0 },
{ "bit\t5, b", 0 },
{ "bit\t5, c", 0 },
{ "bit\t5, d", 0 },
{ "bit\t5, e", 0 },
{ "bit\t5, h", 0 },
{ "bit\t5, l", 0 },
{ "bit\t5, (hl)", 0 },
{ "bit\t5, a", 0 },
{ "bit\t6, b", 0 },
{ "bit\t6, c", 0 },
{ "bit\t6, d", 0 },
{ "bit\t6, e", 0 },
{ "bit\t6, h", 0 },
{ "bit\t6, l", 0 },
{ "bit\t6, (hl)", 0 },
{ "bit\t6, a", 0 },
{ "bit\t7, b", 0 },
{ "bit\t7, c", 0 },
{ "bit\t7, d", 0 },
{ "bit\t7, e", 0 },
{ "bit\t7, h", 0 },
{ "bit\t7, l", 0 },
{ "bit\t7, (hl)", 0 },
{ "bit\t7, a", 0 },
{ "res\t0, b", 0 },
{ "res\t0, c", 0 },
{ "res\t0, d", 0 },
{ "res\t0, e", 0 },
{ "res\t0, h", 0 },
{ "res\t0, l", 0 },
{ "res\t0, (hl)", 0 },
{ "res\t0, a", 0 },
{ "res\t1, b", 0 },
{ "res\t1, c", 0 },
{ "res\t1, d", 0 },
{ "res\t1, e", 0 },
{ "res\t1, h", 0 },
{ "res\t1, l", 0 },
{ "res\t1, (hl)", 0 },
{ "res\t1, a", 0 },
{ "res\t2, b", 0 },
{ "res\t2, c", 0 },
{ "res\t2, d", 0 },
{ "res\t2, e", 0 },
{ "res\t2, h", 0 },
{ "res\t2, l", 0 },
{ "res\t2, (hl)", 0 },
{ "res\t2, a", 0 },
{ "res\t3, b", 0 },
{ "res\t3, c", 0 },
{ "res\t3, d", 0 },
{ "res\t3, e", 0 },
{ "res\t3, h", 0 },
{ "res\t3, l", 0 },
{ "res\t3, (hl)", 0 },
{ "res\t3, a", 0 },
{ "res\t4, b", 0 },
{ "res\t4, c", 0 },
{ "res\t4, d", 0 },
{ "res\t4, e", 0 },
{ "res\t4, h", 0 },
{ "res\t4, l", 0 },
{ "res\t4, (hl)", 0 },
{ "res\t4, a", 0 },
{ "res\t5, b", 0 },
{ "res\t5, c", 0 },
{ "res\t5, d", 0 },
{ "res\t5, e", 0 },
{ "res\t5, h", 0 },
{ "res\t5, l", 0 },
{ "res\t5, (hl)", 0 },
{ "res\t5, a", 0 },
{ "res\t6, b", 0 },
{ "res\t6, c", 0 },
{ "res\t6, d", 0 },
{ "res\t6, e", 0 },
{ "res\t6, h", 0 },
{ "res\t6, l", 0 },
{ "res\t6, (hl)", 0 },
{ "res\t6, a", 0 },
{ "res\t7, b", 0 },
{ "res\t7, c", 0 },
{ "res\t7, d", 0 },
{ "res\t7, e", 0 },
{ "res\t7, h", 0 },
{ "res\t7, l", 0 },
{ "res\t7, (hl)", 0 },
{ "res\t7, a", 0 },
{ "set\t0, c", 0 },
{ "set\t0, d", 0 },
{ "set\t0, e", 0 },
{ "set\t0, h", 0 },
{ "set\t0, l", 0 },
{ "set\t0, (hl)", 0 },
{ "set\t0, a", 0 },
{ "set\t1, b", 0 },
{ "set\t1, c", 0 },
{ "set\t1, d", 0 },
{ "set\t1, e", 0 },
{ "set\t1, h", 0 },
{ "set\t1, l", 0 },
{ "set\t1, (hl)", 0 },
{ "set\t1, a", 0 },
{ "set\t2, b", 0 },
{ "set\t2, c", 0 },
{ "set\t2, d", 0 },
{ "set\t2, e", 0 },
{ "set\t2, h", 0 },
{ "set\t2, l", 0 },
{ "set\t2, (hl)", 0 },
{ "set\t2, a", 0 },
{ "set\t3, b", 0 },
{ "set\t3, c", 0 },
{ "set\t3, d", 0 },
{ "set\t3, e", 0 },
{ "set\t3, h", 0 },
{ "set\t3, l", 0 },
{ "set\t3, (hl)", 0 },
{ "set\t3, a", 0 },
{ "set\t4, b", 0 },
{ "set\t4, c", 0 },
{ "set\t4, d", 0 },
{ "set\t4, e", 0 },
{ "set\t4, h", 0 },
{ "set\t4, l", 0 },
{ "set\t4, (hl)", 0 },
{ "set\t4, a", 0 },
{ "set\t5, b", 0 },
{ "set\t5, c", 0 },
{ "set\t5, d", 0 },
{ "set\t5, e", 0 },
{ "set\t5, h", 0 },
{ "set\t5, l", 0 },
{ "set\t5, (hl)", 0 },
{ "set\t5, a", 0 },
{ "set\t6, b", 0 },
{ "set\t6, c", 0 },
{ "set\t6, d", 0 },
{ "set\t6, e", 0 },
{ "set\t6, h", 0 },
{ "set\t6, l", 0 },
{ "set\t6, (hl)", 0 },
{ "set\t6, a", 0 },
{ "set\t7, b", 0 },
{ "set\t7, c", 0 },
{ "set\t7, d", 0 },
{ "set\t7, e", 0 },
{ "set\t7, h", 0 },
{ "set\t7, l", 0 },
{ "set\t7, (hl)", 0 },
{ "set\t7, a", 0 },
];

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