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clean up mod.rs
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@sigil-03
sigil-03 committed Aug 14, 2024
1 parent b360ab3 commit 39d0a9f
Showing 1 changed file with 0 additions and 169 deletions.
169 changes: 0 additions & 169 deletions src/common/can/mod.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -69,119 +69,6 @@ pub enum Error {
/// enum
EmbeddedHal(embedded_hal::ErrorKind),
}

/// Unclocked Can modules
///
/// The `Unclocked` struct represents the unconfigured Can peripherals.
/// Once clocked, you'll have the ability to build Can peripherals from the
// /// compatible processor pins.
// pub struct Unclocked {
// pub(crate) can1: ral::can::Instance<1>,
// pub(crate) can2: ral::can::Instance<2>,
// }

// impl Unclocked {
// /// Enable clocks to all Can modules, returning a builder for the two Can modules.
// pub fn clock(
// self,
// // handle: &mut ccm::Handle,
// handle: &mut ral::ccm::RegisterBlock,
// clock_select: ccm::can::ClockSelect,
// divider: ccm::can::PrescalarSelect,
// ) -> (Builder<1>, Builder<2>) {
// let ccm = handle;

// // First, disable the clocks for Can1 and Can2
// ral::modify_reg!(
// ral::ccm,
// ccm,
// CCGR0,
// CG7: 0b00,
// CG8: 0b00,
// CG9: 0b00,
// CG10: 0b00
// );

// let clk_sel = match clock_select {
// ccm::can::ClockSelect::OSC => ral::ccm::CSCMR2::CAN_CLK_SEL::RW::CAN_CLK_SEL_1,
// };

// // Select clock, and commit prescalar
// ral::modify_reg!(
// ral::ccm,
// ccm,
// CSCMR2,
// CAN_CLK_PODF: ral::ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_1,
// CAN_CLK_SEL: clk_sel
// );

// // Enable the clocks for Can1 and Can2
// ral::modify_reg!(
// ral::ccm,
// ccm,
// CCGR0,
// CG7: 0b11,
// CG8: 0b11,
// CG9: 0b11,
// CG10: 0b11
// );

// let source_clock = clock_select as u32 / divider as u32;
// (
// Builder::new(source_clock, self.can1),
// Builder::new(source_clock, self.can2),
// )
// }
// }

// /// A CAN peripheral which is temporarily disabled.
// pub struct Disabled<'a, const N: u8> {
// can: &'a ral::can::Instance<N>,
// men: bool,
// }

// impl<'a, const N: u8> Disabled<'a, N> {
// fn new(can: &'a mut ral::can::Instance<N>) -> Self {
// let men = ral::read_reg!(ral::can, can, MCR, MEN == MEN_1);

// // Request disable
// ral::modify_reg!(ral::lpspi, lpspi, CR, MEN: MEN_0);
// // Wait for the driver to finish its current transfer
// // and enter disabled state
// while ral::read_reg!(ral::lpspi, lpspi, CR, MEN == MEN_1) {}
// Self { can, mode, men }
// }
// }

// /// A Can builder that can build a Can peripheral
// pub struct Builder<const M: u8> {
// _module: PhantomData<ral::can::Instance<M>>,
// reg: ral::can::Instance<M>,
// clock_frequency: u32,
// }

// impl<const M: u8> Builder<M> {
// fn new(clock_frequency: u32, reg: ral::can::Instance<M>) -> Self {
// Builder {
// _module: PhantomData,
// reg,
// clock_frequency,
// }
// }

// // /// Builds a Can peripheral.
// // pub fn build<TX, RX>(self, mut tx: TX, mut rx: RX) -> CAN<M>
// // where
// // TX: flexcan::Pin<Module = ral::can::Instance<M>, Signal = flexcan::Tx>,
// // RX: flexcan::Pin<Module = ral::can::Instance<M>, Signal = flexcan::Rx>,
// // {
// // imxrt_iomuxc::flexcan::prepare(&mut tx);
// // imxrt_iomuxc::flexcan::prepare(&mut rx);

// // CAN::new(self.clock_frequency, self.reg)
// // }
// }

pub struct Pins<Tx, Rx> {
/// CAN TX Pin
pub tx: Tx,
Expand Down Expand Up @@ -233,67 +120,11 @@ where
can.begin();
can
}

// fn enable_clocks(
// handle: &mut ral::ccm::RegisterBlock,
// clock_select: ccm::can::ClockSelect,
// divider: ccm::can::PrescalarSelect,
// ) -> u32 {
// let ccm = handle;

// // First, disable the clocks for Can1 and Can2
// ral::modify_reg!(
// ral::ccm,
// ccm,
// CCGR0,
// CG7: 0b00,
// CG8: 0b00,
// CG9: 0b00,
// CG10: 0b00
// );

// let clk_sel = match clock_select {
// ccm::can::ClockSelect::OSC => ral::ccm::CSCMR2::CAN_CLK_SEL::RW::CAN_CLK_SEL_1,
// };

// // Select clock, and commit prescalar
// ral::modify_reg!(
// ral::ccm,
// ccm,
// CSCMR2,
// CAN_CLK_PODF: ral::ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_1,
// CAN_CLK_SEL: clk_sel
// );

// // Enable the clocks for Can1 and Can2
// ral::modify_reg!(
// ral::ccm,
// ccm,
// CCGR0,
// CG7: 0b11,
// CG8: 0b11,
// CG9: 0b11,
// CG10: 0b11
// );

// let source_clock = clock_select as u32 / divider as u32;
// }
}

impl<P, const M: u8> CAN<P, M> {
pub const NUMBER_FIFO_RX_MAILBOXES: u32 = 6;

// fn new(clock_frequency: u32, reg: ral::can::Instance<M>) -> Self {
// let mut can = CAN {
// reg,
// _module: PhantomData,
// clock_frequency,
// _mailbox_reader_index: 0,
// };
// can.begin();
// can
// }

pub fn print_registers(&self) {
// log::info!("MCR: {:X}", ral::read_reg!(ral::can, self.reg, MCR));
// log::info!("CTRL1: {:X}", ral::read_reg!(ral::can, self.reg, CTRL1));
Expand Down

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