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Finomnis committed Nov 24, 2023
1 parent 47ff70a commit c4d938d
Showing 1 changed file with 6 additions and 1 deletion.
7 changes: 6 additions & 1 deletion src/common/lpspi/bus.rs
Original file line number Diff line number Diff line change
Expand Up @@ -49,6 +49,7 @@ impl<'a, const N: u8> Lpspi<'a, N> {
tx_fifo_size,
};

// Reset, enable master mode
ral::write_reg!(ral::lpspi, this.lpspi(), CR, RST: RST_1);
ral::write_reg!(ral::lpspi, this.lpspi(), CR, RST: RST_0);
ral::write_reg!(
Expand All @@ -58,12 +59,14 @@ impl<'a, const N: u8> Lpspi<'a, N> {
MASTER: MASTER_1,
SAMPLE: SAMPLE_1
);

// Set sane default parameters
this.disabled(|bus| {
// Sane defaults
bus.set_clock_hz(1_000_000);
bus.set_mode(MODE_0)
});

// Configure pins
lpspi::prepare(&mut pins.sdo);
lpspi::prepare(&mut pins.sdi);
lpspi::prepare(&mut pins.sck);
Expand All @@ -73,6 +76,8 @@ impl<'a, const N: u8> Lpspi<'a, N> {
RXWATER: this.rx_fifo_size / 2 - 1, // always divisible by two
TXWATER: this.tx_fifo_size / 2 - 1
);

// Enable
ral::write_reg!(ral::lpspi, this.lpspi(), CR, MEN: MEN_1);

this
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