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Merge pull request #30 from ronghongbo/master
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Update T2S tutorials' READMEs: no need to specify a10 or s10 when calling setenv.sh
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ronghongbo authored May 21, 2021
2 parents a6640bb + ff74e62 commit 8f08a0e
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2 changes: 1 addition & 1 deletion main/QuickStartGuides/T2S/README.md
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Expand Up @@ -33,7 +33,7 @@ T2S enables software programmers to build systolic arrays on Intel FPGAs for bot
```
cd tutorials
source /data/t2s/setenv.sh a10 # s10 if you chose a node with Stratix 10.
source /data/t2s/setenv.sh
```
+ Play with a tutorial.
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2 changes: 1 addition & 1 deletion main/QuickStartGuides/T2S/tutorials/fpga/capsule/README.md
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Expand Up @@ -18,7 +18,7 @@ Paul and Michael find it not easy to implement Capsule kernel in existing framew

## Set up the environment according to [instructions]().

Basically, enter a working directory, and `source /data/t2s/setenv.sh a10 (or s10)` to set up the environment. The environment is determined based on the specific FPGA model (a10 or s10), and the version of the Intel FPGA SDK for OpenCL compiler (i.e. version of aoc).
Basically, enter a working directory, and `source /data/t2s/setenv.sh` to set up the environment. The environment is determined based on the specific FPGA model (a10 or s10), and the version of the Intel FPGA SDK for OpenCL compiler (i.e. version of aoc).

## How to design a systolic array?

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2 changes: 1 addition & 1 deletion main/QuickStartGuides/T2S/tutorials/fpga/pairhmm/README.md
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Expand Up @@ -47,7 +47,7 @@ For implementing the PairHMM algorithm, the above equations are all we need, and

## Set up the environment according to [instructions]().

Basically, enter a working directory, and `source /data/t2s/setenv.sh a10 (or s10)` to set up the environment. The environment is determined based on the specific FPGA model (a10 or s10), and the version of the Intel FPGA SDK for OpenCL compiler (i.e. version of aoc).
Basically, enter a working directory, and `source /data/t2s/setenv.sh` to set up the environment. The environment is determined based on the specific FPGA model (a10 or s10), and the version of the Intel FPGA SDK for OpenCL compiler (i.e. version of aoc).

## How to design a systolic array?

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