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main/QuickStartGuides/Workshop_Simulation_Debug_Remote/Lab_1/Simulation_Example.qar
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main/QuickStartGuides/Workshop_Simulation_Debug_Remote/Lab_1/tb_counter.v
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`timescale 1ns/10ps //Time precision | ||
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module testbench(); | ||
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//declare inputs as reg and connect to top module | ||
//declare outputs as wire and connect to top module | ||
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//Instantiation of top module | ||
top t1( .refclk() , .reset_pll() ,.reset_count(), .check() , .Count_up() , .Count_down() ); | ||
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initial | ||
begin | ||
//Initialize inputs as 0 | ||
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/* Set inputs as 1,0 after different time intervals to check the functionality of testbench */ | ||
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#1000 $finish; //$finish to finish simulation or $stop to stop simulation. | ||
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end | ||
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always #10 clock = ~clock; //50 MHz Clock (20 ns clock period), many ways to write the clock | ||
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endmodule |
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...StartGuides/Workshop_Simulation_Debug_Remote/Lab_2/Example_ISSP_SignalTap_CVGXStarter.qar
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main/QuickStartGuides/Workshop_Simulation_Debug_Remote/Simulation-Lab_3101_Manual.docx
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main/QuickStartGuides/Workshop_Simulation_Debug_Remote/Simulation-Lab_3101_Manual.pdf
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...ckStartGuides/Workshop_Simulation_Debug_Remote/Solution/Example_ISSP_SignalTap_solution.v
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module Counter ( | ||
input clock, | ||
input reset, | ||
output reg [6:0] Ones_Display, | ||
output reg [6:0] Tens_Display | ||
); | ||
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reg [23:0] delay; //Delay variable for the counter values to get displayed on the seven segment (Like clock divider) | ||
reg [3:0] Ones_Counter = 4'b0; //counter_ones variable | ||
reg [3:0] Tens_Counter = 4'b0; //counter_tens variable | ||
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always @(posedge clock) | ||
begin | ||
if(reset == 1'b0) //if reset set variables to 0 | ||
begin | ||
Ones_Counter <= 0; | ||
delay <=0; | ||
Tens_Counter <=0; | ||
end | ||
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else | ||
begin | ||
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delay <= delay +1; //increment delay each cycle | ||
if ((delay == 24'b100000000000000000000000) && (Ones_Counter <= 4'b1001) ) | ||
begin | ||
Ones_Counter <= Ones_Counter + 1; //increment ones_counter once delay reached its value & increment tens_counter | ||
if(Ones_Counter == 4'b1001) | ||
begin | ||
Tens_Counter<= Tens_Counter +1; | ||
end | ||
end | ||
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else if(Ones_Counter > 4'b1001) //Rollover to zero | ||
Ones_Counter <= 4'b0000; | ||
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else if(Tens_Counter > 4'b1001) //Rollover to zero | ||
Tens_Counter <=4'b0000; | ||
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end | ||
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case(Ones_Counter) //Seven Segment decoder | ||
4'b0000: Ones_Display <= 7'b1000000; // "0" | ||
4'b0001: Ones_Display <= 7'b1111001; // "1" | ||
4'b0010: Ones_Display <= 7'b0100100; // "2" | ||
4'b0011: Ones_Display <= 7'b0110000; // "3" | ||
4'b0100: Ones_Display <= 7'b0011001; // "4" | ||
4'b0101: Ones_Display <= 7'b0010010; // "5" | ||
4'b0110: Ones_Display <= 7'b0000010; // "6" | ||
4'b0111: Ones_Display <= 7'b1111000; // "7" | ||
4'b1000: Ones_Display <= 7'b0000000; // "8" | ||
4'b1001: Ones_Display <= 7'b0010000; // "9" | ||
default: Ones_Display <= 7'b1000000; // "0" | ||
endcase | ||
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case(Tens_Counter) //Seven Segment Decoder | ||
4'b0000: Tens_Display <= 7'b1000000; // "0" | ||
4'b0001: Tens_Display <= 7'b1111001; // "1" | ||
4'b0010: Tens_Display <= 7'b0100100; // "2" | ||
4'b0011: Tens_Display <= 7'b0110000; // "3" | ||
4'b0100: Tens_Display <= 7'b0011001; // "4" | ||
4'b0101: Tens_Display <= 7'b0010010; // "5" | ||
4'b0110: Tens_Display <= 7'b0000010; // "6" | ||
4'b0111: Tens_Display <= 7'b1111000; // "7" | ||
4'b1000: Tens_Display <= 7'b0000000; // "8" | ||
4'b1001: Tens_Display <= 7'b0010000; // "9" | ||
default: Tens_Display <= 7'b1000000; // "0" | ||
endcase | ||
end | ||
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endmodule | ||
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main/QuickStartGuides/Workshop_Simulation_Debug_Remote/Solution/tb_counter_solution.v
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`timescale 1ns/10ps | ||
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module tb_counter(); | ||
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reg clock,reset_pll,reset_count,counter_direction; | ||
wire [3:0] count_up , count_down; | ||
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top_counter DUT ( .refclk(clock) , | ||
.reset_pll(reset_pll) , | ||
.reset_count(reset_count), | ||
.counter_direction(counter_direction), | ||
.count_up(count_up), | ||
.count_down(count_down) ); | ||
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initial | ||
begin | ||
clock = 0; | ||
reset_pll =1; | ||
reset_count=1; | ||
counter_direction =0; | ||
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#10 reset_pll=0; | ||
#30 reset_count=0; | ||
#10 counter_direction=1; | ||
#30 counter_direction=0; | ||
#10 counter_direction=1; | ||
#30 counter_direction=0; | ||
#10 counter_direction=1; | ||
#30 counter_direction=0; | ||
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#1000 $stop; | ||
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end | ||
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always #10 clock = ~clock; | ||
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endmodule |