virtio: fix potential out of bounds of array access

Signed-off-by: Jiaqi Gao <[email protected]>
intel · May 6, 2024 · f6ac667 · f6ac667
1 parent 986bd71
commit f6ac667
Showing 1 changed file with 5 additions and 3 deletions.
diff --git a/src/devices/virtio/src/virtio_pci.rs b/src/devices/virtio/src/virtio_pci.rs
@@ -62,6 +62,8 @@ use crate::mem;
 use crate::{Result, VirtioError, VirtioTransport};
 use pci::PciDevice;
 
+const VIRTIO_PCI_MAX_CAP_TYPE: usize = 6;
+
 #[allow(clippy::enum_variant_names)]
 enum VirtioPciCapabilityType {
     CommonConfig = 1,
@@ -75,13 +77,13 @@ enum VirtioPciCapabilityType {
 
 #[derive(Default)]
 struct CheckRegionOverlap {
-    flag: [bool; 6],         // VirtioPciCapabilityType max value
-    interval: [[u64; 2]; 6], // VirtioPciCapabilityType max value
+    flag: [bool; VIRTIO_PCI_MAX_CAP_TYPE], // VirtioPciCapabilityType max value
+    interval: [[u64; 2]; VIRTIO_PCI_MAX_CAP_TYPE], // VirtioPciCapabilityType max value
 }
 
 impl CheckRegionOverlap {
     fn set_region(&mut self, index: usize, base: u64, length: u64) -> Result<()> {
-        if index > 6 {
+        if index >= VIRTIO_PCI_MAX_CAP_TYPE {
             return Err(VirtioError::InvalidParameter);
         }