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RISC-V: implement helper
#loadConstant64:into:
This commit implements `TRRV64GCodeGenerator >> #loadConstant64:into:` that loads 64bit signed integer into given register. The code is almost literal translation of code in OMR, see `compiler/riscv/codegen/OMRTreeEvaluator.cpp`, `loadConstant64()`.
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Original file line number | Diff line number | Diff line change |
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Extension { #name : #Integer } | ||
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{ #category : #'*Tinyrossa' } | ||
Integer >> extractBitsFrom: hiBit to: loBit [ | ||
"Extracts (hiBit,loBit) from 64bit value, starting at bit 'hiBit'. Lowest bit is bit 0, | ||
* highest bit is bit 63. This method assumes the receiver is 64bit unsigned integer value. | ||
Return value is also 'unsigned', that is, greater than zero. | ||
" | ||
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self assert: (self between: 0 and: 16rFFFFFFFFFFFFFFFF). | ||
self assert: hiBit < 64. | ||
self assert: (loBit between: 0 and: hiBit). | ||
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^ (self >> loBit) & (16rFFFFFFFFFFFFFFFF << (hiBit - loBit + 1)) bitInvert. | ||
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" | ||
(16rCAFEBABE extractBitsFrom: 15 to: 8) hex | ||
(16rCAFE00AFFE00BABE extractBitsFrom: 47 to: 24) hex | ||
(16rCAFE00AFFE00BABE extractBitsFrom: 57 to: 57) hex | ||
" | ||
] |
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