RISC-V: implement idiv and ldiv evaluators

janvrany · Sep 3, 2024 · 97bf98c · 97bf98c
1 parent 5400117
commit 97bf98c
Showing 1 changed file with 41 additions and 0 deletions.
diff --git a/src/Tinyrossa-RISCV/TRRV64GCodeEvaluator.class.st b/src/Tinyrossa-RISCV/TRRV64GCodeEvaluator.class.st
@@ -41,6 +41,37 @@ TRRV64GCodeEvaluator >> commonBin: node opcodeR: opR opcodeI: opI [
 	^ dstReg
 ]
 
+{ #category : #'evaluation-helpers' }
+TRRV64GCodeEvaluator >> commonDiv: node [
+	"Handles imul and lmul"
+
+	| child1 child2 src1Reg src2Reg dstReg |
+
+	child1 := node child1.
+	child2 := node child2.
+
+	src1Reg := self evaluate: child1.
+
+	(child2 opcode isLoadConst and: [child2 constant == 1]) ifTrue:[
+		dstReg := src1Reg.
+	] ifFalse:[
+	(child2 opcode isLoadConst and: [child2 constant == -1]) ifTrue:[
+			dstReg := self codegen allocateRegister.
+			generate sub: dstReg, zero, src1Reg
+	] ifFalse:[
+		src2Reg := self evaluate: child2.
+		dstReg := self codegen allocateRegister.
+
+		node type == Int64 ifTrue:[
+			generate div: dstReg, src1Reg , src2Reg
+		] ifFalse:[
+			generate divw: dstReg, src1Reg , src2Reg
+		].
+	]].
+
+	^dstReg
+]
+
 { #category : #'evaluation-helpers' }
 TRRV64GCodeEvaluator >> commonLoad: node [
 	"Handles aload, lload, iload, sload & bload"  
@@ -429,6 +460,11 @@ TRRV64GCodeEvaluator >> evaluate_iconst: node [
 	^ dstReg
 ]
 
+{ #category : #evaluation }
+TRRV64GCodeEvaluator >> evaluate_idiv: node [
+	^self commonDiv: node.
+]
+
 { #category : #'evaluation-helpers' }
 TRRV64GCodeEvaluator >> evaluate_ifXcmpeq: node [
 	"Handles Address, Int64 Int32, Int16 & Int8"  
@@ -675,6 +711,11 @@ TRRV64GCodeEvaluator >> evaluate_lconst: node [
 	^ dstReg
 ]
 
+{ #category : #evaluation }
+TRRV64GCodeEvaluator >> evaluate_ldiv: node [
+	^self commonDiv: node.
+]
+
 { #category : #evaluation }
 TRRV64GCodeEvaluator >> evaluate_lload: node [
 	^ self commonLoad: node