Merge pull request #29 from janvrany/pr/misc-improvements-07

Misc improvements 7
janvrany · Oct 8, 2023 · e313019 · e313019
2 parents e12f653 + d4be1ee
commit e313019
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Showing 14 changed files with 96 additions and 47 deletions.
diff --git a/.gitignore b/.gitignore
@@ -14,6 +14,7 @@ pharo/lib
 pharo/Pharo*.zip
 pharo/*.o
 pharo/*.s
+pharo/github-cache
 
 # Smalltalk/X
 stx/stx
@@ -38,6 +39,5 @@ shell-*
 *.orig
 
 # Gem5 by-products
-stx/m5out
-pharo/m5out
+m5out
 
diff --git a/shell/GNUmakefile b/shell/GNUmakefile
@@ -13,7 +13,7 @@ CROSS?=$(ARCH)-linux-gnu-
 all: shell-$(ARCH)
 
 shell-$(ARCH): shell.c shell.link
-	$(CROSS)gcc -ggdb2 -O2 -static -T shell.link -o $@ $<
+	$(CROSS)gcc -ggdb2 -O0 -static -T shell.link -o $@ $<
 
 endif
 

diff --git a/shell/shell.c b/shell/shell.c
@@ -1,25 +1,54 @@
 #include <stdio.h>
 #include <stdlib.h>
+#include <errno.h>
 
 #define STRINGIFY(x) #x
 #define TOSTRING(x) STRINGIFY(x)
 
 #define NZONE_SIZE 512
 
+#if defined(__x86_64)
+#  define ASM_RETURN "mov %rdi, %rax\nret"
+#elif defined(__riscv)
+#  define ASM_RETURN "ret"
+#elif defined(__powerpc64__)
+#  define ASM_RETURN "blr"
+#else
+#  error "Not (yet) supported architecture"
+#endif
+
 __asm__(
 	"                                  \n"
 	".section .nzone,\"awx\", @progbits\n"
 	"nzone:                            \n"
+	ASM_RETURN "                       \n"
 	".space " TOSTRING(NZONE_SIZE) "   \n"
 	"                                  \n"
 	".section .text                    \n"
 );
 
 extern unsigned char nzone[NZONE_SIZE];
 
-typedef int (*entry_func)();
+typedef int (*entry_func)(int a);
 static entry_func entry = (entry_func)(&nzone);
 
-int main() {
-	return entry();
+static int __attribute__ ((noinline)) trampoline(int a) {
+	return entry(a);
+}
+
+int main(int argc, char** argv) {
+	int x = 0;
+	switch (argc) {
+		case 1:
+			x = 42;
+			break;
+		case 2:
+			x = strtol(argv[1], NULL, 10);
+			if (errno) return 127;
+			break;
+		default:
+			 return 127;
+			 break;
+	}
+	return trampoline(x);
 }
diff --git a/src/Tinyrossa-POWER/TRPPC64CodeEvaluator.class.st b/src/Tinyrossa-POWER/TRPPC64CodeEvaluator.class.st
@@ -2,8 +2,8 @@ Class {
 	#name : #TRPPC64CodeEvaluator,
 	#superclass : #TRCodeEvaluator,
 	#pools : [
-		'TRPPC64Registers',
-		'TRPPC64RegisterKinds'
+		'TRPPC64RegisterKinds',
+		'TRPPC64Registers'
 	],
 	#category : #'Tinyrossa-POWER-Codegen'
 }

diff --git a/src/Tinyrossa-POWER/TRPPC64CodeGenerator.class.st b/src/Tinyrossa-POWER/TRPPC64CodeGenerator.class.st
@@ -2,12 +2,12 @@ Class {
 	#name : #TRPPC64CodeGenerator,
 	#superclass : #TRCodeGenerator,
 	#classVars : [
-		'MinDFormImm',
-		'MaxDFormImm'
+		'MaxDFormImm',
+		'MinDFormImm'
 	],
 	#pools : [
-		'TRPPC64Registers',
-		'TRIntLimits'
+		'TRIntLimits',
+		'TRPPC64Registers'
 	],
 	#category : #'Tinyrossa-POWER-Codegen'
 }

diff --git a/src/Tinyrossa-POWER/TRPPC64PSABILinkage.class.st b/src/Tinyrossa-POWER/TRPPC64PSABILinkage.class.st
@@ -17,12 +17,12 @@ Class {
 		'BackChainOffset',
 		'CRSaveWordOffset',
 		'LRSaveDoublewordOffset',
-		'TOCPointerDoublewordOffset',
-		'ParameterSaveAreaOffset'
+		'ParameterSaveAreaOffset',
+		'TOCPointerDoublewordOffset'
 	],
 	#pools : [
-		'TRPPC64Registers',
-		'TRDataTypes'
+		'TRDataTypes',
+		'TRPPC64Registers'
 	],
 	#category : #'Tinyrossa-POWER-Codegen'
 }

diff --git a/src/Tinyrossa-POWER/TRPPC64RegisterKinds.class.st b/src/Tinyrossa-POWER/TRPPC64RegisterKinds.class.st
@@ -2,9 +2,9 @@ Class {
 	#name : #TRPPC64RegisterKinds,
 	#superclass : #TRSharedPool,
 	#classVars : [
-		'GPR',
+		'CCR',
 		'FPR',
-		'CCR'
+		'GPR'
 	],
 	#category : #'Tinyrossa-POWER-Codegen'
 }

diff --git a/src/Tinyrossa-RISCV/TRRV64GCodeEvaluator.class.st b/src/Tinyrossa-RISCV/TRRV64GCodeEvaluator.class.st
@@ -2,8 +2,8 @@ Class {
 	#name : #TRRV64GCodeEvaluator,
 	#superclass : #TRCodeEvaluator,
 	#pools : [
-		'TRRV64GRegisters',
-		'TRDataTypes'
+		'TRDataTypes',
+		'TRRV64GRegisters'
 	],
 	#category : #'Tinyrossa-RISCV-Codegen'
 }
@@ -454,6 +454,21 @@ TRRV64GCodeEvaluator >> evaluate_lload: node [
 	^ dstReg
 ]
 
+{ #category : #evaluation }
+TRRV64GCodeEvaluator >> evaluate_lmul: node [
+	^self emitMul: node.
+]
+
+{ #category : #evaluation }
+TRRV64GCodeEvaluator >> evaluate_lor: node [
+	^self emitBin: node opcodeR: 'or' opcodeI: 'ori'
+]
+
+{ #category : #evaluation }
+TRRV64GCodeEvaluator >> evaluate_lshr: node [
+	^self emitShr: node
+]
+
 { #category : #evaluation }
 TRRV64GCodeEvaluator >> evaluate_lstore: node [
 	| symbol srcReg |
@@ -464,6 +479,11 @@ TRRV64GCodeEvaluator >> evaluate_lstore: node [
 	^ nil
 ]
 
+{ #category : #evaluation }
+TRRV64GCodeEvaluator >> evaluate_lsub: node [
+	^self emitBin: node opcodeR: 'sub' opcodeI: 'addi'
+]
+
 { #category : #evaluation }
 TRRV64GCodeEvaluator >> evaluate_sconst: node [
 	^ self evaluate_iconst: node

diff --git a/src/Tinyrossa-RISCV/TRRV64GCodeGenerator.class.st b/src/Tinyrossa-RISCV/TRRV64GCodeGenerator.class.st
@@ -2,9 +2,9 @@ Class {
 	#name : #TRRV64GCodeGenerator,
 	#superclass : #TRCodeGenerator,
 	#pools : [
-		'TRRV64GRegisters',
 		'TRIntLimits',
-		'TRRV64GISALimits'
+		'TRRV64GISALimits',
+		'TRRV64GRegisters'
 	],
 	#category : #'Tinyrossa-RISCV-Codegen'
 }

diff --git a/src/Tinyrossa-RISCV/TRRV64GISALimits.class.st b/src/Tinyrossa-RISCV/TRRV64GISALimits.class.st
@@ -3,8 +3,8 @@ Class {
 	#superclass : #TRSharedPool,
 	#classVars : [
 		'RISCV_IMM_BITS',
-		'RISCV_IMM_MIN',
-		'RISCV_IMM_MAX'
+		'RISCV_IMM_MAX',
+		'RISCV_IMM_MIN'
 	],
 	#category : #'Tinyrossa-RISCV-Codegen'
 }

diff --git a/src/Tinyrossa-RISCV/TRRV64GPSABILinkage.class.st b/src/Tinyrossa-RISCV/TRRV64GPSABILinkage.class.st
@@ -12,8 +12,8 @@ Class {
 		'framePreservedOffset'
 	],
 	#pools : [
-		'TRRV64GRegisters',
-		'TRIntLimits'
+		'TRIntLimits',
+		'TRRV64GRegisters'
 	],
 	#category : #'Tinyrossa-RISCV-Codegen'
 }

diff --git a/src/Tinyrossa-RISCV/TRRV64GRegisters.class.st b/src/Tinyrossa-RISCV/TRRV64GRegisters.class.st
@@ -2,16 +2,6 @@ Class {
 	#name : #TRRV64GRegisters,
 	#superclass : #TRSharedPool,
 	#classVars : [
-		'zero',
-		'ra',
-		'sp',
-		'gp',
-		'tp',
-		't0',
-		't1',
-		't2',
-		's0',
-		's1',
 		'a0',
 		'a1',
 		'a2',
@@ -20,6 +10,12 @@ Class {
 		'a5',
 		'a6',
 		'a7',
+		'gp',
+		'ra',
+		's0',
+		's1',
+		's10',
+		's11',
 		's2',
 		's3',
 		's4',
@@ -28,12 +24,16 @@ Class {
 		's7',
 		's8',
 		's9',
-		's10',
-		's11',
+		'sp',
+		't0',
+		't1',
+		't2',
 		't3',
 		't4',
 		't5',
-		't6'
+		't6',
+		'tp',
+		'zero'
 	],
 	#pools : [
 		'TRRegisterKinds'

diff --git a/src/Tinyrossa/TRILOpcodeTables.class.st b/src/Tinyrossa/TRILOpcodeTables.class.st
@@ -2,17 +2,17 @@ Class {
 	#name : #TRILOpcodeTables,
 	#superclass : #TRSharedPool,
 	#classVars : [
-		'LoadOpcodes',
-		'StoreOpcodes',
-		'ConstOpcodes',
+		'ArithmeticOpcodes',
 		'CompareOpcodes',
-		'ArithmeticOpcodes'
+		'ConstOpcodes',
+		'LoadOpcodes',
+		'StoreOpcodes'
 	],
 	#pools : [
-		'TRILOpcodes',
 		'TRDataTypes',
 		'TRILOpcodeProps1',
-		'TRILOpcodeProps3'
+		'TRILOpcodeProps3',
+		'TRILOpcodes'
 	],
 	#category : #'Tinyrossa-IL'
 }

diff --git a/src/Tinyrossa/TRILSimplifier.class.st b/src/Tinyrossa/TRILSimplifier.class.st
@@ -9,10 +9,10 @@ Class {
 		'ConditionalBranchSimplificationTable'
 	],
 	#pools : [
-		'TRILOpcodes',
 		'TRDataTypes',
 		'TRILOpcodeProps1',
-		'TRILOpcodeProps3'
+		'TRILOpcodeProps3',
+		'TRILOpcodes'
 	],
 	#category : #'Tinyrossa-Optimizer'
 }