Issue#26: Adding parsing of Vivado Methodology report file.

docs/source/vendors/xilinx/vivado_methodology.rst

@@ -0,0 +1,43 @@
+Vivado Methodology
+~~~~~~~~~~~~~~~~~~
+
+The Vivado methologoy report has a single warning format, but two different type of warnings:  critical warnings and non critical warnings.
+Some warning messages can also span multiple lines.
+
+Methodology Format
+^^^^^^^^^^^^^^^^^^
+
+Each methodology violation is reported over multiple lines.
+
+<ID>#<count> <classification>
+<description>
+<details>
+Related violations: <related>
+
+where:
+
++-------------------------------+-------------------------------------------------+
+| Item                          |  Regular Expression Match                       |
++===============================+=================================================+
+| ID                            | \W+                                             |
++-------------------------------+-------------------------------------------------+
+| count                         | [0-9]+                                          |
++-------------------------------+-------------------------------------------------+
+| classification                | \W+                                             |
++-------------------------------+-------------------------------------------------+
+| details                       | \\W+\s\W+                                       |
++-------------------------------+-------------------------------------------------+
+| related                       | \\W+\s\W+                                       |
++-------------------------------+-------------------------------------------------+
+
+Extracting Warnings
+^^^^^^^^^^^^^^^^^^^
+
+Extraction of warnings from the logfile will follow this process:
+
+1.  Search for second line starting with 2. REPORT DETAILS
+2.  Extract ID and drop count and classification
+3.  drop description
+4.  Extract details
+5.  drop related
+

docs/source/vendors/xilinx/xilinx.rst

@@ -2,5 +2,6 @@ Xilinx
 ------
 
 .. include:: vivado.rst
+.. include:: vivado_methodology.rst
 
 

elfws/vendor/xilinx/vivado_methodology.py

@@ -0,0 +1,68 @@
+from elfws import warning
+from elfws import warning_list
+
+
+def get_vendor():
+    return ['Xilinx']
+
+
+def get_tool_name():
+    return 'vivado'
+
+
+def is_logfile(lFile):
+    bSearch = False
+    for iLineNumber, sLine in enumerate(lFile):
+        if 'Tool Version' in sLine and 'Vivado' in sLine:
+            bSearch = True
+        if bSearch and sLine.startswith('Report Methodology'):
+            return True
+        if iLineNumber == 200:
+            return False
+    return False
+
+
+def extract_warnings(lFile):
+    oReturn = warning_list.create()
+
+    lRules = extract_rule_ids_from_summary(lFile)
+    iNumSection = 0
+    iWarningLine = 0
+    for iLineNumber, sLine in enumerate(lFile):
+
+        if iWarningLine == 0:
+            for sRule in lRules:
+                if sLine.startswith(sRule):
+                    iWarningLine = 1
+                    sID = sRule
+
+        if iWarningLine == 1:
+            iWarningLine += 1
+        elif iWarningLine == 2:
+            iWarningLine += 1
+        elif iWarningLine == 3:
+            sMessage = sLine
+            iWarningLine += 1
+        elif iWarningLine == 4:
+            iWarningLine = 0
+            oWarning = warning.create(sID, sMessage, None, iLineNumber - 2) 
+            oReturn.add_warning(oWarning)
+
+    return oReturn
+
+
+def extract_rule_ids_from_summary(lFile):
+    iNumSection = 0
+    iTableDivider = 0
+    lReturn = []
+    for sLine in lFile:
+        if iTableDivider == 3:
+            break
+        if iTableDivider == 2 and not sLine.startswith('+---'):
+            lLine = sLine.split()
+            lReturn.append(lLine[1])
+        if iNumSection == 2 and sLine.startswith('+---'):
+            iTableDivider += 1 
+        if sLine.startswith('1. REPORT SUMMARY'):
+            iNumSection += 1 
+    return lReturn

tests/vendor/xilinx/vivado_methodology/test_functions.py

@@ -0,0 +1,134 @@
+import os
+import unittest
+
+from elfws.vendor.xilinx import vivado_methodology
+from tests import test_utils
+
+lLogFile = test_utils.read_file(os.path.join(os.path.dirname(__file__), 'warning_messages.rpt'))
+
+class testFunctions(unittest.TestCase):
+
+    def test_extract_warnings(self):
+        oWarningList = vivado_methodology.extract_warnings(lLogFile)
+
+        oWarning = oWarningList.warnings[0]
+        self.assertEqual('TIMING-18', oWarning.get_id())
+        self.assertEqual('An input delay is missing on I_CS_F relative to clock(s) I_CLK', oWarning.get_message())
+        self.assertEqual(None, oWarning.get_filename())
+        self.assertEqual(37, oWarning.get_linenumber())
+
+        oWarning = oWarningList.warnings[1]
+        self.assertEqual('TIMING-18', oWarning.get_id())
+        self.assertEqual('An input delay is missing on I_DATA relative to clock(s) I_CLK', oWarning.get_message())
+        self.assertEqual(None, oWarning.get_filename())
+        self.assertEqual(42, oWarning.get_linenumber())
+
+        oWarning = oWarningList.warnings[2]
+        self.assertEqual('TIMING-18', oWarning.get_id())
+        self.assertEqual('An input delay is missing on I_MISO_DATA relative to clock(s) I_CLK', oWarning.get_message())
+        self.assertEqual(None, oWarning.get_filename())
+        self.assertEqual(47, oWarning.get_linenumber())
+
+        oWarning = oWarningList.warnings[3]
+        self.assertEqual('TIMING-18', oWarning.get_id())
+        self.assertEqual('An input delay is missing on I_RST relative to clock(s) I_CLK', oWarning.get_message())
+        self.assertEqual(None, oWarning.get_filename())
+        self.assertEqual(52, oWarning.get_linenumber())
+
+        oWarning = oWarningList.warnings[4]
+        self.assertEqual('TIMING-18', oWarning.get_id())
+        self.assertEqual('An input delay is missing on I_SCK relative to clock(s) I_CLK', oWarning.get_message())
+        self.assertEqual(None, oWarning.get_filename())
+        self.assertEqual(57, oWarning.get_linenumber())
+
+        oWarning = oWarningList.warnings[5]
+        self.assertEqual('TIMING-18', oWarning.get_id())
+        self.assertEqual('An output delay is missing on O_DATA relative to clock(s) I_CLK', oWarning.get_message())
+        self.assertEqual(None, oWarning.get_filename())
+        self.assertEqual(62, oWarning.get_linenumber())
+
+        oWarning = oWarningList.warnings[6]
+        self.assertEqual('TIMING-18', oWarning.get_id())
+        self.assertEqual('An output delay is missing on O_MOSI_CLK relative to clock(s) I_CLK', oWarning.get_message())
+        self.assertEqual(None, oWarning.get_filename())
+        self.assertEqual(67, oWarning.get_linenumber())
+
+        oWarning = oWarningList.warnings[7]
+        self.assertEqual('TIMING-19', oWarning.get_id())
+        self.assertEqual('An output delay is missing on O_MOSI_CS_F relative to clock(s) I_CLK', oWarning.get_message())
+        self.assertEqual(None, oWarning.get_filename())
+        self.assertEqual(72, oWarning.get_linenumber())
+
+        oWarning = oWarningList.warnings[8]
+        self.assertEqual('TIMING-20', oWarning.get_id())
+        self.assertEqual('An output delay is missing on O_MOSI_DATA relative to clock(s) I_CLK', oWarning.get_message())
+        self.assertEqual(None, oWarning.get_filename())
+        self.assertEqual(77, oWarning.get_linenumber())
+
+        self.assertEqual(9, oWarningList.get_number_of_warnings())
+
+    def test_is_logfile(self):
+        lLogFile = []
+        lLogFile.append('Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.')
+        lLogFile.append('-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------')
+        lLogFile.append('| Tool Version : Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020')
+        lLogFile.append('| Date         : Sun Aug 13 10:00:30 2023')
+        lLogFile.append('| Host         : DESKTOP-HV9NHA3 running 64-bit major release  (build 9200)')
+        lLogFile.append('| Command      : report_methodology -file four_wire_spi_methodology_drc_routed.rpt -pb four_wire_spi_methodology_drc_routed.pb -rpx four_wire_spi_methodology_drc_routed.rpx')
+        lLogFile.append('| Design       : four_wire_spi')
+        lLogFile.append('| Device       : xa7a12tcpg238-2I')
+        lLogFile.append('| Speed File   : -2I')
+        lLogFile.append('| Design State : Fully Routed')
+        lLogFile.append('-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------')
+        lLogFile.append(' ')
+        lLogFile.append('Report Methodology')
+
+        self.assertTrue(vivado_methodology.is_logfile(lLogFile))
+
+        lLogFile = []
+        lLogFile.append('***** Vivado v2018.3 (64-bit)')
+        lLogFile.append('  **** SW Build 2405991 on ')
+        lLogFile.append('  **** IP Build 2404404 on ')
+        lLogFile.append('   ** Copyright ')
+
+        self.assertFalse(vivado_methodology.is_logfile(lLogFile))
+
+        lLogFile = []
+        lLogFile.append(' ')
+        lLogFile.append(' ')
+        lLogFile.append('***** Vivado v2018.3 (64-bit)')
+        lLogFile.append('  **** SW Build 2405991 on ')
+        lLogFile.append('  **** IP Build 2404404 on ')
+        lLogFile.append('   ** Copyright ')
+        lLogFile.append(' ')
+        lLogFile.append(' ')
+        lLogFile.append(' ')
+        lLogFile.append(' ')
+        lLogFile.append(' ')
+        lLogFile.append(' ')
+        lLogFile.append(' ')
+        lLogFile.append(' ')
+
+        self.assertFalse(vivado_methodology.is_logfile(lLogFile))
+
+        lLogFile = []
+        for i in range(0, 100):
+            lLogFile.append('  ')
+        lLogFile.append('# Vivado ')
+        lLogFile.append('# SW Build ')
+        lLogFile.append('# IP Build ')
+        lLogFile.append('# Process ID: ')
+
+        self.assertFalse(vivado_methodology.is_logfile(lLogFile))
+
+        lLogFile = []
+        for i in range(0, 300):
+            lLogFile.append('')
+
+        self.assertFalse(vivado_methodology.is_logfile(lLogFile))
+
+    def test_vendor(self):
+        self.assertEqual(['Xilinx'], vivado_methodology.get_vendor())
+
+    def test_tool_name(self):
+        self.assertEqual('vivado', vivado_methodology.get_tool_name())

tests/vendor/xilinx/vivado_methodology/warning_messages.rpt

@@ -0,0 +1,82 @@
+Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
+| Date         : Sun Aug 13 10:00:30 2023
+| Host         : DESKTOP-HV9NHA3 running 64-bit major release  (build 9200)
+| Command      : report_methodology -file four_wire_spi_methodology_drc_routed.rpt -pb four_wire_spi_methodology_drc_routed.pb -rpx four_wire_spi_methodology_drc_routed.rpx
+| Design       : four_wire_spi
+| Device       : xa7a12tcpg238-2I
+| Speed File   : -2I
+| Design State : Fully Routed
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Report Methodology
+
+Table of Contents
+-----------------
+1. REPORT SUMMARY
+2. REPORT DETAILS
+
+1. REPORT SUMMARY
+-----------------
+            Netlist: netlist
+          Floorplan: design_1
+      Design limits: <entire design considered>
+             Max violations: <unlimited>
+             Violations found: 9
++-----------+----------+-------------------------------+------------+
+| Rule      | Severity | Description                   | Violations |
++-----------+----------+-------------------------------+------------+
+| TIMING-18 | Warning  | Missing input or output delay | 7          |
+| TIMING-19 | Warning  | Missing input or output delay | 1          |
+| TIMING-20 | Warning  | Missing input or output delay | 1          |
++-----------+----------+-------------------------------+------------+
+
+2. REPORT DETAILS
+-----------------
+TIMING-18#1 Warning
+Missing input or output delay  
+An input delay is missing on I_CS_F relative to clock(s) I_CLK
+Related violations: <none>
+
+TIMING-18#2 Warning
+Missing input or output delay  
+An input delay is missing on I_DATA relative to clock(s) I_CLK
+Related violations: <none>
+
+TIMING-18#3 Warning
+Missing input or output delay  
+An input delay is missing on I_MISO_DATA relative to clock(s) I_CLK
+Related violations: <none>
+
+TIMING-18#4 Warning
+Missing input or output delay  
+An input delay is missing on I_RST relative to clock(s) I_CLK
+Related violations: <none>
+
+TIMING-18#5 Warning
+Missing input or output delay  
+An input delay is missing on I_SCK relative to clock(s) I_CLK
+Related violations: <none>
+
+TIMING-18#6 Warning
+Missing input or output delay  
+An output delay is missing on O_DATA relative to clock(s) I_CLK
+Related violations: <none>
+
+TIMING-18#7 Warning
+Missing input or output delay  
+An output delay is missing on O_MOSI_CLK relative to clock(s) I_CLK
+Related violations: <none>
+
+TIMING-19#1 Warning
+Missing input or output delay  
+An output delay is missing on O_MOSI_CS_F relative to clock(s) I_CLK
+Related violations: <none>
+
+TIMING-20#1 Warning
+Missing input or output delay  
+An output delay is missing on O_MOSI_DATA relative to clock(s) I_CLK
+Related violations: <none>
+
+