- SiEPIC-Tools - for silicon photonics layout, design, verification and circuit simulation
- Developed by Lukas Chrostowski, with contributions by: Zeqin Lu, Jaspreet Jhoja, Xu Wang, Jonas Flueckiger, and others.
- This is a package implemented using Python in KLayout.
- Instruction on design, layout, fabrication, test, data analysis for silicon photonics provided in the edX course: Silicon Photonics Design, Fabrication and Data Analysis and textbook Silicon Photonics Design: From Devices to Systems by Lukas Chrostowski and Michael Hochberg.
- Fabrication runs via Electron Beam Lithography are available, including the University of Washington, Applied Nanotools Inc., and SiEPICfab.
- Process Design Kits that use KLayout SiEPIC-Tools are available for multiple foundries including AMF, AIM Photonics.
- Citing this work:
- Lukas Chrostowski, Zeqin Lu, Jonas Flueckiger, Xu Wang, Jackson Klein, Amy Liu, Jaspreet Jhoja, James Pond, "Design and simulation of silicon photonic schematics and layouts," Proc. SPIE 9891, Silicon Photonics and Photonic Integrated Circuits V, 989114 (May 13, 2016); doi:10.1117/12.2230376.
- Lukas Chrostowski, Hossam Shoman, Mustafa Hammood, Han Yun, Jaspreet Jhoja, Enxiao Luan, Stephen Lin, Ajay Mistry, Donald Witt, Nicolas A. F. Jaeger, Sudip Shekhar, Hasitha Jayatilleka, Philippe Jean, Simon B.-de Villers, Jonathan Cauchon, Wei Shi, Cameron Horvath, Jocelyn N. Westwood-Bachman, Kevin Setzer, Mirwais Aktary, N. Shane Patrick, Richard Bojko, Amin Khavasi, Xu Wang, Thomas Ferreira de Lima, Alexander N. Tait, Paul R. Prucnal, David E. Hagan, Doris Stevanovic, Andy P. Knights, "Silicon Photonic Circuit Design Using Rapid Prototyping Foundry Process Design Kits" IEEE Journal of Selected Topics in Quantum Electronics, Volume: 25, Issue: 5, Sept.-Oct. 2019. (PDF)
- in KLayout v0.27, use Tools | Package Manager, and find SiEPIC-Tools there (more details in the Wiki Instructions)
- install PDK, e.g., SiEPIC_EBeam_PDK download and installation instructions on the wiki page.
- Use an open-source layout tool (KLayout) to implement a sophisticated layout design environment for silicon photonics
- Support for both GUI and Python script-based layout, or combinations of both.
- KLayout-INTERCONNECT integration offers a layout-first design methodology. Inspired by Layout Versus Schematic tools, this includes netlist extraction routines to generate a schematic from the layout. This allows the user to directly simulate from the layout, without needing to create the schematic first. This approach is appealing to photonics designers who are accustomed to designing physical layouts, rather than schematics. A library of components (layout and compact models) is included in the SiEPIC-EBeam-PDK Process Design Kit, specifically for silicon photonics fabrication via Electron Beam Lithography.
- Whereas a typical schematic-driven design flow includes a schematic, circuit simulation, layout, and verification (see Chapter 10 of the textbook), the approach taken here is Layout-driven, followed by verification, then a schematic (via a netlist extraction) and simulations.
Video of a layout and simulation of a ring resonator circuit:
Monte Carlo simulations of a ring resonator circuit, showing fabrication variations:
Layout of a Mach-Zehnder Interferometer:
Simulations for the MZI:
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Generic Silicon Photonics (GSiP) Process Design Kit (PDK): this package, including fabrication documentation, scripts, etc.
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PCells: ring modulator
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GDS Library: grating coupler, detector, edge coupler.
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Verification:
- Scanning the layout. Finding waveguides, devices, pins.
- Verification: Identifying if there are missing connections, mismatched waveguides, too few points in a bend, etc.
- Example layouts using the library for verification (EBeam_LukasChrostowski_E_LVS.gds, SiEPIC_EBeam_PDK_Verification_Check.gds).
- Verification for automated measurements
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Circuit simulations:
- Netlist generation
- Creating a Spice netlist suitable for for circuit simulations. This includes extracting the waveguide length (wg_length) for all waveguides.
- Menu item "Lumerical INTERCONNECT" will automatically: generate the netlist, launch Lumerical INTERCONNECT to perform the circuit simulations, and pop-up a plot of the transmission spectrum.
- Monte Carlo simulations, including waveguides, ring resonators built using directional couplers, y-branches, grating couplers.
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Waveguide functionality:
- Hot Key "W": selected paths are first snapped to the nearest pins, then converted to waveguides.
- Hot Key "Shift-W": selected waveguides are converted back to paths.
- Hot Key "Ctrl-Shift-W": measure the length of the selected waveguides.
- Hot Key "Ctrl-Shift-R": resize the waveguides, for a given target length.
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Layout object snapping
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Hot Key "Shift-O": Snaps the selected object to the one where the mouse is hovering over.
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Helper functions from Python-scripted layouts
- snapping components
- adding waveguides between components
- layout primitives (arcs, bezier curves, waveguides, tapers, rings, etc)
You can download the latest development version (master) of the PDK: Zip file download of the PDK
It is posted on GitHub for 1) revision control, 2) so that others can contribute to it, find bugs, 3) easy download of the latest version.
To contribute to the PDK:
- On the GitHub web page, Fork a copy of the project into your own account.
- Clone to your Desktop
- Make edits/contributions. You can use the KLayout IDE to write Python (or Ruby) scripts; KLayout Python IDE for writing/debugging PCells/scripts/macros.
- "Commit to master" (your own master)
- Create a Pull Request -- this will notify me of your contribution, which I can merge into the main project
You can use GitHub desktop to synchronize files. Then create symbolic links to your .klayout folder to point to the local copy of this repository. This is useful to automatically update the local KLayout installation (e.g., multiple computers), as changes are made in GitHub by others.
