3.1 VFB6 LVDS

This example implementation of the jTDC is designed for the VFB6 board from ELB using 3 LVDS input mezzanine cards. It's inputs and outputs are mapped as follows:

• MEZA: LVDS input channel 01-32
• MEZB: LVDS input channel 33-64
• MEZC: LVDS input channel 65-96
• NIM[0]: Channel 0 input (trigger and busy) input (frontpanel, left NIM socket)
• NIM[1]: Trigger A output (frontpanel, right NIM socket)
• NIM[2]: Channel 97 input (backpanel, left NIM socket)
• NIM[3]: Trigger B output (backpanel, right NIM socket)

All registers are 32bit registers and you must read/write all 32bits, even if you want to change/set/get only a specific bit. Some registers are so called toggle registers, they toggle back to 0x00000000 after one clock cycle and are used to trigger events (for example resets). The read value from such a toggle register has mostly a completely different source (for example status information) and has nothing to do with the toggle state of the register.

3.1.1 Enable registers

address	32bit bitmask to enable/disable channels
0xbase2000	LVDS input channels 32 - 01
0xbase2004	LVDS input channels 64 - 33
0xbase2008	LVDS input channels 96 - 65

This is a configuration register, you can readback the current values at any given time.

3.1.2 Config register A @ 0xbase0020

bits	config value
4-0	Set GeoID of the module. This ID is written into the header data of each event.
5	Set to 1 to enable dutycycle count mode (check input state each clk cycle and count if state is high)
6	Set to 1 to invert all inputs
7	Set to 1 to use LVDS_A_IN[0] instead of NIM[0] as trigger input
15-8	Set maximum trigger window size to (N*5)ns (max 1250ns)

This is a configuration register, you can readback the current values at any given time.

3.1.3 Config register B @ 0xbase0028

bits	config value
8-0	busyshift** (0-2500ns in steps of 5ns)
9	enable lifetime gate for counters (stop counting on busy)**
15-11	busyextend (0-155ns in steps of 5ns, must not be larger than length of busy)**
19-16	lifetime (length) setting for trigger output: (5*N + 10)ns
23-20	deadtime setting for trigger output: (5*N + 10)ns
26-24	3bit mask for trigger output NIM[1] to select OR of LVDS_C, LVDS_B and/or LVDS_A (0x7 will put the logical OR of all LVDS inputs on NIM[1], 0x2 just those of LVDS_B)
29-27	3bit mask for trigger output NIM[3] to select OR of LVDS_C, LVDS_B and/or LVDS_A (0x7 will put the logical OR of all LVDS inputs on NIM[3], 0x2 just those of LVDS_B)
30	disable external latch (scalers will not be latched by the trigger input)

This is a configuration register, you can readback the current values at any given time.

** The trigger-input is used twofold: Its leading edge is used as trigger and its length is used as DAQ deadtime/busy indicator. If the DAQ keeps the trigger signal active until it has finished processing it (read-out of all TDCs), the jTDC can use that information as a life-time-gate for its input scalers. To cope with extra delay due to cables and other elements, the busy signal can be shifted and extended.

3.1.4 Trigger register @ 0xbase0024

bit	toggle actions
0	TDC reset
1	counter reset
2	counter latch
3	output reset (must be called after changing the high- or dead time settings, and after initial fw load)

This is a toggle register, the readback value of this register contains the following information:

bit	value
7-0	firmware version
15-8	module id
23-16	number of encoded bits per channel
31-24	number of tdc channels

3.1.5 Scaler read-out registers

CAUTION! The scalers cannot be addressed directly! First read the clock counter and then read register 0xbase4000 98 times to get the 98 scaler values. For convenience, the addressbus is masked for register 0xbase4000, so one could also consecutively read address 0xbase4000 to 0xbase409B.

address	value in read-only register
0xbase0044	clock counter (a read request sets the current read-out scaler to channel 0)
0xbase4000	scaler value of the current read-out scaler (auto incrementation of the current read-out scaler)