Canny-FPGA-Pipe is a VHDL implementation of the Canny edge detector. It has a pipelined architecture and is designed for a resolution of 640x480 pixels.
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Canny-FPGA-Pipe: a pipelined Canny edge detector implementation for FPGAs
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kornerc/Canny-FPGA-Pipe
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Canny-FPGA-Pipe: a pipelined Canny edge detector implementation for FPGAs
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