Update faster, README, tests

.travis.yml

@@ -30,8 +30,13 @@ matrix:
     - rust: nightly
       env:
         - ARCH=x86_64
-        - FEATURES="--features avx-accel"
-        - RUSTFLAGS="-C target-feature=+avx"
+        - FEATURES="--features simd-accel"
+        - RUSTFLAGS="-C target-feature=+sse4.2"
+    - rust: nightly
+      env:
+        - ARCH=x86_64
+        - FEATURES="--features simd-accel"
+        - RUSTFLAGS="-C target-cpu=native"
 addons:
   apt:
     packages:

Cargo.toml

@@ -18,7 +18,7 @@ bench = false
 simd-accel = ["faster"]
 
 [dependencies]
-faster = { version = "0.4.2", optional = true }
+faster = { version = "0.4.3", optional = true }
 
 [dev-dependencies]
 quickcheck = "0.6"

README.md

@@ -28,28 +28,21 @@ fn main() {
 }
 ```
 
-bytecount supports two features to make use of modern CPU's features to speed up counting considerably. To allow your
-users to use them, add the following to your `Cargo.toml`:
+bytecount makes use of features in modern CPUs to speed up counting considerably. To use these features,
+add the following to your `Cargo.toml`:
 
 ```
 [features]
-avx-accel = ["bytecount/avx-accel"]
 simd-accel = ["bytecount/simd-accel"]
 ```
 
-Now your users can compile with SSE support (available on most modern x86_64 processors) using:
+Now your users can compile with SIMD support, regardless of processor type, using:
 
 ```
-cargo build --release --features simd-accel
+RUSTFLAGS="-C target-cpu=native" cargo build --release --features simd-accel
 ```
 
-Or even with AVX support (which likely requires compiling for the native target CPU):
-
-```
-RUSTFLAGS="-C target-cpu=native" cargo build --release --features "simd-accel avx-accel"
-```
-
-The algorithm is explained in depth
+The scalar algorithm is explained in depth
 [here](https://llogiq.github.io/2016/09/27/count.html).
 
 Note that for very short slices, the data parallelism will likely not win much performance gains. In those cases, a naive