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Updated verilator waivers so the sim builds.
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Signed-off-by: Hugo McNally <[email protected]>
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HU90m committed Jan 31, 2024
1 parent 2039880 commit e9e4d52
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Showing 2 changed files with 4 additions and 2 deletions.
4 changes: 3 additions & 1 deletion dv/verilator/demo_system_verilator_lint.vlt
Original file line number Diff line number Diff line change
Expand Up @@ -25,4 +25,6 @@ lint_off -rule PINMISSING -file "*pulp_riscv_dbg*"
lint_off -rule UNUSED -file "*ibex_register_file_fpga*"

lint_off -rule UNOPTFLAT -file "*/lowrisc_prim_fifo_0/rtl/prim_fifo_async_simple.sv"
lint_off -rule WIDTHEXPAND -file "*pulp_riscv_dbg/src/dm_mem.sv"
lint_off -rule WIDTH -file "*pulp_riscv_dbg/src/dm_mem.sv"
lint_off -rule UNDRIVEN -file "*ibex_register_file_fpga.sv"
lint_off -rule IMPERFECTSCH -file "*prim_flop_2sync.sv"
2 changes: 1 addition & 1 deletion ibex_demo_system_core.core
Original file line number Diff line number Diff line change
Expand Up @@ -24,7 +24,7 @@ filesets:

files_lint_verilator:
files:
- lint/verilator_waiver.vlt: {file_type: vlt}
- vendor/lowrisc_ibex/lint/verilator_waiver.vlt: {file_type: vlt}

targets:
default:
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