describe a clock divider must use blocking

assignment

VerilogCodingStyle.md

@@ -1756,13 +1756,14 @@ an always block as occurring in a separate simulation event as the non-blocking
 assignment. This process makes some signals jump registers, potentially leading
 to total protonic reversal. That's bad.
 
-Exception: For a clock divider blocking assingment must be used not to case race condition.
+Note that all clock signals should be generated using blocking assignment even
+for clock dividers. See #44 for details.
 
 👍
 ```systemverilog {.good}
 logic clk_div2;
 always_ff @(posedge clk or negedge rst_ni) begin
-  // only for a clock divider blocking assignment must be used not to cause race condition
+  // a clock signal should be generated using blocking assignment
   if (!rst_ni) clk_div2 = 1'b0;
   else         clk_div2 = ~clk_div2;
 end