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This repository has been archived by the owner on May 5, 2024. It is now read-only.

Releases: makslevental/openhls

BraggNN works at 5,4

29 Aug 17:02
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Router Utilization Summary
  Global Vertical Routing Utilization    = 23.6995 %
  Global Horizontal Routing Utilization  = 24.2244 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 0
    (Failed Nets is the sum of unrouted and partially routed nets)
  Number of Unrouted Nets             = 0
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 0
+----------------------------+-------+--------+--------+--------+--------+--------+
|          Site Type         |  SLR0 |  SLR1  |  SLR2  | SLR0 % | SLR1 % | SLR2 % |
+----------------------------+-------+--------+--------+--------+--------+--------+
| CLB                        |  6732 |  53635 |  53940 |  12.25 |  99.32 |  99.89 |
|   CLBL                     |  3802 |  29110 |  29262 |  12.98 |  99.42 |  99.94 |
|   CLBM                     |  2930 |  24525 |  24678 |  11.41 |  99.21 |  99.83 |
| CLB LUTs                   | 23341 | 333954 | 383162 |   5.31 |  77.30 |  88.69 |
|   LUT as Logic             | 23341 | 333954 | 383162 |   5.31 |  77.30 |  88.69 |
|     using O5 output only   |    24 |    615 |    270 |  <0.01 |   0.14 |   0.06 |
|     using O6 output only   | 20743 | 290124 | 337009 |   4.72 |  67.16 |  78.01 |
|     using O5 and O6        |  2574 |  43215 |  45883 |   0.59 |  10.00 |  10.62 |
|   LUT as Memory            |     0 |      0 |      0 |   0.00 |   0.00 |   0.00 |
|     LUT as Distributed RAM |     0 |      0 |      0 |   0.00 |   0.00 |   0.00 |
|     LUT as Shift Register  |     0 |      0 |      0 |   0.00 |   0.00 |   0.00 |
| CLB Registers              | 18691 | 333209 | 377577 |   2.13 |  38.57 |  43.70 |
| CARRY8                     |   244 |   5184 |   5184 |   0.44 |   9.60 |   9.60 |
| F7 Muxes                   |     0 |      0 |      0 |   0.00 |   0.00 |   0.00 |
| F8 Muxes                   |     0 |      0 |      0 |   0.00 |   0.00 |   0.00 |
| F9 Muxes                   |     0 |      0 |      0 |   0.00 |   0.00 |   0.00 |
| Block RAM Tile             |     0 |      0 |      0 |   0.00 |   0.00 |   0.00 |
|   RAMB36/FIFO              |     0 |      0 |      0 |   0.00 |   0.00 |   0.00 |
|   RAMB18                   |     0 |      0 |      0 |   0.00 |   0.00 |   0.00 |
| URAM                       |     0 |      0 |      0 |   0.00 |   0.00 |   0.00 |
| DSPs                       |     0 |      0 |      0 |   0.00 |   0.00 |   0.00 |
| Unique Control Sets        |   200 |   3988 |   2999 |   0.18 |   3.69 |   2.78 |
+----------------------------+-------+--------+--------+--------+--------+--------+
    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
      0.008        0.000                      0              1050116        0.023        0.000                      0              1050116        4.725        0.000                       0                729477  

BraggNN passes testbench

27 Aug 17:25
029b257
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Merge pull request #3 from makslevental/max_op

Max op

First successful synth, place, and route of BraggNN

first release 🙌✊🥳🎉👏

02 Aug 15:17
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Get setup.py working