Update dependency edu.berkeley.cs:chisel3-plugin to v3.6.1 #9
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This PR contains the following updates:
3.5.0-RC2->3.6.1Release Notes
chipsalliance/chisel (edu.berkeley.cs:chisel3-plugin)
v3.6.1: Chisel v3.6.1Compare Source
Features
CHISEL_USE_COLOR. Set totrueto force Chisel to use color andfalseto disable it.TERMto be set to something other thandumb.This
SyncReadMemwrapper is instantiated using a new object,SRAM.apply, and invokes.write,.read, and.readWriteto generate a desired number of read, write, and read/write ports. This function returns a newBundlewire containing the control signals for each requested port.SRAM.applyandSRAM.maskednow take acontentsparameter, by default aNone, which is a string path to a binary file on the filesystem which the SRAM should be initialized with.Add new
SRAMAPIs that take threeClocksequences as parameters instead of the number of read/write/read-write ports. This will sequentially instantiate a memory port for each clock in theClocksequence and drive them accordingly.Adds
suggestNameAPI for hierarchy instances.This gives a flexible way to generate a stable name for a Chisel type, which is useful for problems like generating stable names for
ModulesandQueuesAPI Deprecation
Also fix a crash that could occur when viewing a non-Data containing non-hardware Data.
Backend Code Generation
This results in a slight improvement to emitted FIRRTL quality
Performance
Fixes
SyncReadMem.readWritewhen explicit clocks are used (backport #3313) (by @mergify[bot] inhttps://github.com/chipsalliance/chisel/pull/33155)Chisel will to report multiple errors, but this can be cut short by any thrown Exception which would then take precedence over the previously encountered errors. Now Chisel will prioritize reporting errors even if an Exception is thrown.
Fixes a bug in D/I where unsanitary names would lead to a crash. It also makes the Printable output for Bundles and Records use the sanitary names which makes them better match the FIRRTL.
This fixes Scala compiler warnings in Scala 2.13.12 requiring type ascriptions on public implicit definitions.
Reg()to properly handle clocks as rvalues (backport #3775) (by @mergify[bot] inhttps://github.com/chipsalliance/chisel/pull/37788)DataView(includingFlatIO)Reg()Previously, the function would infinitely recurse resulting in a stack overflow.
Previously, the user-specified (or unspecified minimum width) of the literal would be used in some operations like concatenation. For literal values that are too-wide, they will now truncate to the correct width. This will become a warning (then later an error) in newer major versions of Chisel.
Documentation
Just a oneline fix to the comment of Arbiter chosen port
Update CONTRIBUTING instructions to clarify backport process and branch to target.
Existing links to
https://github.com/chipsalliance/chisel/releases/latest/download/chisel-template.scalashould instead usehttps://github.com/chipsalliance/chisel/releases/latest/download/chisel-example.scalaDependency Updates
Build and Internal Changes
Improve backport automation so that release notes generation from backport PRs works properly.
import chisel3._import chisel3.util._mikepenz/release-changelog-builder-actionto v4.1.1Full Changelog: chipsalliance/chisel@v3.6.0...v3.6.1
v3.6.0: Chisel v3.6.0Compare Source
The primary change in Chisel v3.6.0 is the transition from the Scala FIRRTL Compiler to the new MLIR FIRRTL Compiler. This will have a minimal impact on typical Chisel user APIs but a large impact on custom compiler flows. For more information, please see the ROADMAP.
Try it out using this Scastie! Also check out the API Docs.
Highlights
Deprecations
Note that many more deprecations are coming before the release of 3.6.0.
import Chisel._)import firrtl._)chisel3.internal, these should never have been publicFor users who wish to continue using the Scala FIRRTL Compiler or other removed APIs for the time being, please see Migration Off Deprecated Features below.
Removals
Many APIs deprecated in Chisel 3.5 have been removed in Chisel 3.6.
This includes (but is not limited to):
cloneTypeis now generated forRecords, it is an error to implementcloneTypemanuallyMultiIOModule(useModule).asUInt()is removed, use.asUInt)RawModule.getPortsandchisel3.getModulePortsstopwith non-zero return codeprintf,assert, andassume) will error if you use aDatain an s-interpolated String (s"..."), usecf"..."instead.Performance Improvements
The MLIR FIRRTL Compiler is much faster than the Scala FIRRTL Compiler (3-7x). Users should should substantial speedups by switching to using MFC.
In addition, while there have been many performance improvements to Chisel itself included in the 3.5 release line, there are some new improvements that only apply to 3.6. Preliminary results show a speedup of 22% and 5% reduction in heap use. These results are sensitive to particular user designs so actual results may vary.
_idsdatastructure to reduce its size: https://github.com/chipsalliance/chisel3/pull/2866IO(Input(UInt(8.W)))will now create only a singleUIntobject instead of 3Other Changes
InstantiateAPI for multiply instantiating moduleschisel3chisel3.experimental.ChiselEnumwas moved to packagechisel3Migration from Chisel 3.5
3.6.0 includes everything from 3.5.6 and before. Some features are newly deprecated in 3.5.6 that are removed in 3.6.0. Please bump to 3.5.6 before attempting to upgrade to 3.6.0.
Migration Off Deprecated Features
All users are encouraged to stop using deprecated features and migrate to the MLIR FIRRTL Compiler; however this may be difficult for some users. For users who depend on deprecated features for which there is no obvious replacement, please reach out to the Chisel developers by filing an issue: https://github.com/chipsalliance/chisel3/issues.
For those who cannot migrate yet and would like to suppress warnings about moving off of the Scala FIRRTL Compiler, you can use Scala's configurable warning support, to suppress the specific warnings. The easiest way to do this is to add the following Scalac option to your build flow:
-Wconf:msg=Importing from firrtl:s". This will silence the warnings telling you to move off of SFC.v3.5.6: Chisel v3.5.6Compare Source
Deprecation
Performance
BugFix
util.exprimental.decode.bitset(#2882)Other
v3.5.5: Chisel v3.5.5Compare Source
Highlights
Users are strongly encouraged to import
chisel3.experimental.AutoCloneTypeand mix it in to theirRecords. Chisel will now print a warning when users implementcloneTypethemselves. It will be an error to implementcloneTypeyourself in Chisel 3.6.Feature
Dataequality (===) via extension method (#2669)Deprecation
Performance
BugFix
Other
v3.5.4: Chisel v3.5.4Compare Source
Feature
cf(#2528)Deprecation
BugFix
Performance
Docs
Other
v3.5.3: Chisel v3.5.3Compare Source
Feature
You can now create IO Bundles that do not have the name of the val as a prefix in the name of the resulting ports. See this Scastie (https://scastie.scala-lang.org/bPg2Kws2QY2rdVyYeENdxw) for an example.
Performance
BugFix
Docs
v3.5.2: Chisel v3.5.2Compare Source
Feature
BugFix
Docs
v3.5.1: Chisel v3.5.1Compare Source
Highlights
The chisel3 compiler plugin can now generate
Bundle.elementswhen-P:chiselplugin:genBundleElementsis passed to Scalac (in SBT this isscalacOptions += "-P:chiselplugin:genBundleElements"). This results in a ~20-30% speedup for Chisel elaboration (excluding FIRRTL). This feature is disabled by default because it is a breaking change to implement elements for any non-final Bundle (a child class extending the given Bundle will rely on the old elementation via inheritance but will now call the newly implemented one in the superclass instead). Users who intend to publish libraries should not enable the feature until updating to Chisel 3.6. Everyone else should use it beginning in Chisel 3.5.1.Memories now bind clocks upon declaration of the memory and not just the ports. It is now a warning for a memory to use differing clocks at declaration time and port creation time unless the differing clock is passed explicitly to the port. For example:
Feature
BugFix
v3.5.0: Chisel v3.5.0Compare Source
Please see the porting guide for upgrading from Chisel 3.4.[1]
Chisel is built on top of FIRRTL so some FIRRTL changes can affect Chisel users, please see the FIRRTL v1.5.0 release notes as well.
Highlights
Data. Often, this is useful for viewing one subtype ofData, as another. One can think about a DataView as a cross between a customizable cast and an untagged union. It enables some very powerful design patterns. Please see the documentation and cookbook for more information. (#1955)Bundlesas if they were an instance of a parent type. It solves a longstanding issue with bulk connectingBundleswhen there is an inheritance relationship between them [#661]. See the DataView cookbook for more details.BundleLiteralsfor creating literal Vecs. Please see the associated documentation for more details. (#1834)import chisel3.experimental.conversions._. See the related section of the DataView explanation for more details. (#2277)Feature
isOneOfmethod toChiselEnum(#1966)API Changes
The chisel3 compiler plugin is now required. See https://github.com/chipsalliance/chisel3#build-your-own-chisel-projects for instructions on how to add it to your project.
.toBools(#2170)This is technically an API change but due to the new chisel3 compiler plugin requirement, it should not affect users
API Deprecations
Deprecate (instead of removing) chisel3.internal.firrtl.Port. Fix deprecation warnings on public APIs that return this type and add ScalaDoc to replacement APIs.
8a73362Remove val io7e4d1eeUpdate docs for the removal of val io and MultiIOModule6c6ec71Fold Chisel.CompatibilityModule into chisel3.internal.LegacyModuleBugFix
import Chisel._. (#2023)?(#2113)Dependency Bumping
Miscellany
verilogmodifier code blocks so that there is always a newline between code blocks and following material. (#2016)-eoption work with ChiselStage methods (#1630)3bea616[plugin] Disable BundleComponent by default, add option to enablea8d3238[plugin] Stop autoclonetype stack traces when using plugin1494231[plugin] Implement autoclonetype in the compiler plugine80e9a3[plugin] Split ChiselComponent into its own file0a0d7c6Make it possible to GC Data instances53b6204Add no-plugin-tests for testing Chisel without the compiler pluginb88ae1fDeprecate override_clock and override_reset in Module5ece5aaRename MultiIOModule to Moduleb96e7ddfarewell Scala 2.11Configuration
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