Fixes

driver/src/main.rs

@@ -6,8 +6,8 @@ extern crate alloc;
 use {
     log::*,
     uefi::prelude::*,
-    hypervisor::vmm::is_hypervisor_present,
-    crate::{virtualize::virtualize_system, capture::{capture_registers, GuestRegisters}},
+    hypervisor::{vmm::is_hypervisor_present, intel::capture::{capture_registers, GuestRegisters}},
+    crate::virtualize::virtualize_system,
 };
 
 pub mod virtualize;

hypervisor/src/intel/ept/mtrr.rs

@@ -43,10 +43,10 @@ impl Mtrr {
 
             // Skip Write Back type as it's the default memory type.
             if item.is_enabled && item.mem_type != MemoryType::WriteBack {
-                let end_address = Self::calculate_end_address(item.base.pa(), item.mask);
+                let end_address = Self::calculate_end_address(item.base, item.mask);
 
                 let descriptor = MtrrRangeDescriptor {
-                    base_address: item.base.pa(),
+                    base_address: item.base,
                     end_address,
                     memory_type: item.mem_type,
                 };

hypervisor/src/intel/mod.rs

@@ -1,6 +1,7 @@
 pub mod capture;
 pub mod controls;
 pub mod descriptor;
+pub mod page;
 pub mod ept;
 //pub mod events;
 //pub mod invept;

hypervisor/src/intel/vm.rs

@@ -33,14 +33,18 @@ pub struct Vm {
 
 impl Vm {
     pub fn new(guest_registers: &GuestRegisters, shared_data: &mut SharedData) -> Self {
-        let mut vmcs = Box::<Vmcs>::default();
+        let vmcs = Box::<Vmcs>::default();
+        let guest_descriptor_table = unsafe { Box::<DescriptorTables>::new_zeroed().assume_init() };
+        let host_descriptor_table = unsafe { Box::<DescriptorTables>::new_zeroed().assume_init() };
         let mut host_paging = unsafe { Box::<PageTables>::new_zeroed().assume_init() };
 
         host_paging.build_identity();
 
         Self {
             vmcs_region: vmcs,
             host_paging,
+            host_descriptor_table,
+            guest_descriptor_table,
             guest_registers: guest_registers.clone(),
             shared_data: unsafe { NonNull::new_unchecked(shared_data as *mut _) },
         }
@@ -63,7 +67,7 @@ impl Vm {
     }
 
     pub fn setup_vmcs(&mut self) -> Result<(), HypervisorError> {
-        Vmcs::setup_guest_registers_state(&self.guest_descriptor_table, &mut self.guest_registers)?;
+        Vmcs::setup_guest_registers_state(&self.guest_descriptor_table, &mut self.guest_registers);
         Vmcs::setup_host_registers_state(&self.host_descriptor_table, &self.host_paging)?;
         Vmcs::setup_vmcs_control_fields(&mut self.shared_data)?;
 

hypervisor/src/intel/vmcs.rs

@@ -61,7 +61,7 @@ impl Vmcs {
         unsafe { vmwrite(vmcs::guest::CR3, controlregs::cr3()) };
         vmwrite(vmcs::guest::CR4, Cr4::read_raw());
 
-        vmwrite(vmcs::guest::DR7, unsafe { dr7().0.bits() });
+        vmwrite(vmcs::guest::DR7, unsafe { dr7().0 as u64 });
 
         vmwrite(vmcs::guest::RSP, guest_registers.rsp);
         vmwrite(vmcs::guest::RIP, guest_registers.rip);

hypervisor/src/intel/vmx.rs

@@ -30,19 +30,19 @@ impl Vmx {
     /// Enables VMX operation by setting appropriate bits and executing the VMXON instruction.
     fn setup_vmxon(&mut self) -> Result<(), HypervisorError> {
         log::trace!("Enabling Virtual Machine Extensions (VMX)");
-        Self::enable_vmx_operation();
+        Vmxon::enable_vmx_operation();
         log::trace!("VMX enabled");
 
         log::trace!("Adjusting IA32_FEATURE_CONTROL MSR");
-        Self::adjust_feature_control_msr()?;
+        Vmxon::adjust_feature_control_msr()?;
         log::trace!("IA32_FEATURE_CONTROL MSR adjusted");
 
         log::trace!("Setting CR0 bits");
-        Self::set_cr0_bits();
+        Vmxon::set_cr0_bits();
         log::trace!("CR0 bits set");
 
         log::trace!("Setting CR4 bits");
-        Self::set_cr4_bits();
+        Vmxon::set_cr4_bits();
         log::trace!("CR4 bits set");
 
         self.vmxon_region.revision_id.set_bit(31, false);

hypervisor/src/intel/vmxon.rs

@@ -33,15 +33,15 @@ impl Default for Vmxon {
 
 impl Vmxon {
     /// Enables VMX operation by setting appropriate bits and executing the VMXON instruction.
-    fn enable_vmx_operation() {
+    pub fn enable_vmx_operation() {
         const CR4_VMX_ENABLE_BIT: usize = 13;
         let mut cr4 = Cr4::read_raw();
         cr4.set_bit(CR4_VMX_ENABLE_BIT, true);
         unsafe { Cr4::write_raw(cr4) };
     }
 
     /// Sets the lock bit in IA32_FEATURE_CONTROL if necessary.
-    fn adjust_feature_control_msr() -> Result<(), HypervisorError> {
+    pub fn adjust_feature_control_msr() -> Result<(), HypervisorError> {
         const VMX_LOCK_BIT: u64 = 1 << 0;
         const VMXON_OUTSIDE_SMX: u64 = 1 << 2;
 
@@ -62,7 +62,7 @@ impl Vmxon {
     }
 
     /// Modifies CR0 to set and clear mandatory bits.
-    fn set_cr0_bits() {
+    pub fn set_cr0_bits() {
         let ia32_vmx_cr0_fixed0 = unsafe { msr::rdmsr(msr::IA32_VMX_CR0_FIXED0) };
         let ia32_vmx_cr0_fixed1 = unsafe { msr::rdmsr(msr::IA32_VMX_CR0_FIXED1) };
 
@@ -75,7 +75,7 @@ impl Vmxon {
     }
 
     /// Modifies CR4 to set and clear mandatory bits.
-    fn set_cr4_bits() {
+    pub fn set_cr4_bits() {
         let ia32_vmx_cr4_fixed0 = unsafe { msr::rdmsr(msr::IA32_VMX_CR4_FIXED0) };
         let ia32_vmx_cr4_fixed1 = unsafe { msr::rdmsr(msr::IA32_VMX_CR4_FIXED1) };