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acronyms.il
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acronyms.il
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(setq acronyms (list nil
'AAP "Analog Auto Placer"
'ABE "Advanced Boolean Engine"
'ADR "Activity-Driven Restructuring"
'AOCV "Advanced On-chip Variation"
'ADE "Analog Design Environment"
'AEL "Analog Expression Language"
'AICM "Automatically-inserted Connect Module"
'AMU "Algorithm Memory Unit"
'AMS "Analog-Mixed-Signal"
'AMSD "AMS Designer"
'AoT "Analog on Top"
'AOI "AND-OR-invert"
'APS "Accelerated Parallel Simulation"
'ATPG "Automatic Test Pattern Generation"
'AVUM "AMS Virtuoso Use Model"
'AWR "Applied Wave Research"
'AXUM "AMS Xcelium Use Model"
'API "Application Programming Interface"
'ALU "Arithmetic Logic Unit"
'ASIC "Application-Specific Integrated Circuit"
'ASG "Automatic Symbol Generator"
'BCWC "Best-Case/Worst-Case"
'BDR "Block-based Discipline Resolution"
'BDU "Blackbox Design Unit"
'BEOL "Back End of Line"
'BER "Bit Error Rate"
'BGA "Ball Grid Array"
'BiCMOS "Bipolar Complementary Metal Oxide Silicon"
'BSIM "Berkeley Short-Channel IGFET Model"
'BIST "Built-in Self Test"
'CAD "Computer Aided Design"
'CAE "Constraint Aware Editing"
'CAN "Cadence Academic Network"
'CAS "Check Against Source"
'CCC "Channel Connected Component"
'CCD "Conformal Constraints Designer"
'CCF "Clock Constraint File"
'CCL "Common Command Language"
'CCOpt "Clock Concurrent Optimization"
'CCR "Cadence Change Request"
'CCS "Composite Current Source"
'CDA "Cadence Doc Assistant"
'CDC "Clock Domain Crossing"
'CDF "Component Description Format"
'CDL "Circuit Description Language"
'CDM "Charge Device Model"
'CDBA "Cadence Database API"
'CDS "Cadence Design Systems"
'CIF "Caltech Intermediate Format"
'CEL "CDF Expression Language"
'CFD "Computational Fluid Dynamics"
'CGIC "Clock-gating integrated cell"
'CIW "Command Interpreter Window"
'CMI "Compile Module Interface"
'CMMMC "Concurrent Multi-Mode Multi Corner"
'CMI "Compile Module Interface"
'CMOS "Complementary Metal Oxide Silicon"
'CMP "Chemical Mechanical Polishing"
'CPF "Common Power Format"
'CDB "Cadence Database"
'CLE "Concurrent Layout Editing"
'CMC "Compact Modeling Counsel"
'CPG "Cadence Placement Guidance"
'CPH "Configure Physical Hierarchy"
'CPPR "Clock Path Pessimism Removal"
'CM "Connect Modules"
'CR "Connect Rules"
'CRPR "Clock Reconvergence Pessimism Removal"
'CSA "Carry-Save Adder"
'CSR "Cadence Space-based Router"
'CTD "Clock Tree Debugger"
'CTS "Clock Tree Synthesis"
'CV "Constraint Validation"
'CVD "Common User Interface"
'DBU "Database Units"
'DCU "Data Compare Unit"
'DDC "Define Device Correspondence"
'DDPI "Design Data Procedural Interface"
'DFII "Design Framework II"
'DFM "Design for Manufacturability"
'DFT "Design for Test"
'DSPF "Detailed Standard Parasitic Format"
'DIBL "Drain-induced barrier lowering"
'DITS "Drain-induced threshold shift"
'DNL "Differential Nonlinearity"
'DMMMC "Distributed Multi-Mode Multi Corner"
'DMIM "Double Metal Insulator Metal"
'DMS "Digital Centric Mixed-Signal"
'DoT "Digital on Top"
'DPO "Dual Port Object"
'DPL "Disembodied Property List"
'DRS "Driver-Receiver Segregation"
'DPT "Double Patterning Technology"
'DR "Discipline Resolution"
'DRC "Design Rule Check"
'DRD "Design Rule Driven"
'DRF "Dynamic Rule Filtering"
'DRL "Device Recognition Layer"
'DRM "Design Rule Manual"
'DRV "Design Rule Violation"
'DSTA "Detaild Standard Parasitic Format"
'DSM "Deep-Submicron"
'DSM "Distributed Static Timing Analysis"
'DUT "Device under Test"
'DVS "Dynamic Voltage Supply"
'ECC "Error-Correcting Codes"
'ECF "Early Clock Flow"
'ECO "Engineering Change Order"
'ECSM "Effective Current Source Model"
'EDA "Electronic Design Automation"
'EDIF "Electronic Design Interchange Format"
'EM "Electromigration"
'EMH "Embedded Module Hierarchy"
'EIP "Edit In Place"
'EIV "Effective Instance Voltage"
'EMIR "Electromigration and IR-Drop"
'ENOB "Effective Number of Bits"
'EOT "Equivalent Oxide Thickness"
'ERA "Early Rail Analysis"
'ERC "Electrical Rule Check"
'ESD "Electrostatic Discharge"
'ESR "Effective Series Resistance"
'ETL "Edge Triggered Latch"
'ETM "Extracted Timing Model"
'FET "Field-Effect Transistor"
'FBB "Forward Body Bias"
'FCU "Fuse Control Unit"
'FEOL "Front End of Line"
'FF "Flip-Flop"
'FGR "Fluid Guard Ring"
'FN "Fowler-Nordheim"
'FNL "Flat Netlister"
'FPGA "Field-Programmable Gate Array"
'FSDB "Fast Signal Database"
'FSM "Finite State Machine"
'FTM "Full Timing Model"
'GBA "Graph-Based Analysis"
'GDM "Generic Design Management"
'GDSII "Graphical Design Station II"
'GFS "Generate From Source"
'GAA_FET "Gates-All-Around FET"
'GIDL "Gate Induced Drain Leakage"
'GISL "Gate Induced Source Leakage"
'GLD "Graphical LVS Debugger"
'GLS "Gate-Level Simulation"
'GPE "Grid Pattern Editor"
'GPH "Generate Physical Hierarchy"
'GPM "Grid Pattern Mapping"
'GSFS "Generate Selected From Source"
'GTD "Global Timing Debug"
'HBT "Hetero-Junction Bipolar Transistor"
'HBM "Human-Body Model"
'HCI "Hot Carrier Injection"
'HDL "Hardware Description Language"
'HED "Hierarchy Editor"
'HMF "Hierarchical Metal Fill Database Flow"
'HNL "Hierarchical Netlister"
'HPB "High Performance Blocking"
'HRCX "Hierarchical Extraction"
'HPM "Hierarchical Pattern Matching"
'IBIS "I/O Buffer Information Specification"
'ICADVM "Integrated Circuit Advanced Node and Advanced Methodologies"
'ILS "Internet Learning Series"
'ILT "Instructor-Led Training"
'ICE "Integration Constraint Editor"
'ICT "Interconnect Technology"
'ICRP "IC Remote Processes"
'ITRS "International Technology Roadmap for Semiconductors"
'IE "Interface Element"
'IGFET "Insulated-Gate Field-Effect Transistor"
'ILD "Inter-Layer Dielectric"
'ILM "Interface Logic Models"
'IPC "Interprocess Communication"
'IOPT "Incremental Optimization"
'ISE "Interactive Simulation Environment"
'IP "Intellectual Property"
'ISL "Interactive Short Locator"
'KCL "Kirchhoff’s Current Law"
'KVL "Kirchhoff’s Voltage Law"
'LDD "Lightly Doped Drain"
'LDE "Layout-Dependent Effects"
'LDS "Low-Discrepancy Sequence"
'LEC "Logic Equivalence Checking"
'LEF "Library Exchange Format"
'LGA "Land Grid Array"
'LHS "Latin Hypercube Sampling"
'LOCOS "Local Oxidation of Silicon"
'LPF "Low Pass Filter"
'LPP "Layer-Purpose Pair"
'LRP "Least Resistive Path"
'LSCS "Large-Scale Cloud Simulation"
'LSF "Load Sharing Facility"
'LTE "Local Truncation Error"
'LVF "Liberty Variation Format"
'LVL "Layout Versus Layout"
'LVS "Layout Versus Schematic"
'MBCI "Multibit Cell Inference"
'MC "Monte Carlo"
'MCP "Multicycle Path"
'MIS "Multi Input Switching"
'MISFET "Metal-Insulator Semiconductor FET"
'MOSFET "Metal-Oxide Semiconductor FET"
'MDL "Measurement Description Language"
'MEOL "Middle End of Line"
'MIM "Metal Insulator Metal"
'MM "Machine Model"
'MMMC "Multi-Mode Multi-Corner"
'MODGEN "Module Generator"
'MPC "Multiple Process Corner"
'MPP "Multipart Path"
'MPT "Multi-Patterning Technology"
'MPW "Multi-Project Wafer"
'MSV "Multiple Supply Voltage"
'MTS "Multi-Technology Simulation"
'NRHF "NanoRoute High Frequency Router"
'NI "National Instruments"
'NTBI "Negative Bias Temperature Instability"
'NLP "Netlist property"
'NLDM "Non-linear Delay Model"
'NQS "Nonquasi-static"
'NT "Near-Threshold"
'OA "Open Access"
'OAI "OR-AND-invert"
'OASIS "Open Artwork System Interchange Standard"
'OBC "One-Button-Checker"
'OCV "On-Chip Variation"
'OOMR "Out-Of-Module Reference"
'OOP "Out-of-Context Probing"
'OPC "Optical Proximity Correction"
'OPCG "On-Product Clock Generation"
'OSSN "Open Simulation System for Netlisting"
'PAE "Process Antenna Effect"
'PBKG "Protected Backgate"
'PDK "Process Design Kit"
'PEX "Parasitic Extraction"
'PIP "Polysilicon Insulator Polysilicon"
'PLA "Programmable Logic Array"
'PLE "Physical Layout Estimation"
'PPA "Performance, Power and Area"
'PR "Place and Route"
'PRO "Process Rule Overrides"
'PBA "Path-Based Analysis"
'PBRS "Pseudo-Random Bit Sequence"
'PBSR "Process-Based Save/Restart"
'PCD "PCell Designer"
'PD "Phase Detector"
'PDP "Power-Delay Product"
'PEEC "Partial Element Equivalent Circuit"
'PERC "Programmable Electrical Rule Check"
'PLCC "Plastic Leadless Chip Carrier"
'PLL "Phase Locked Loop"
'PSF "Parameter Storage Format"
'PSN "Power Supply Network"
'PSS "Periodic Steady State"
'PMBIST "Programmable Memory Built-In Self-Test"
'PTAM "Power Test Access Mechanism"
'PVL "Physical Verification Language"
'PVS "Physical Verification Solution"
'PVT "Process, Voltage and Temperature"
'QOR "Quality of Results"
'QRC "Quantus Extraction Solution"
'RAK "Rapid Adoption Kit"
'RAP "Rapid Analog Prototype"
'RAU "Redundancy Analysis Unit"
'RIP "Receiver Input Peak Check"
'RNM "Real Number Modeling"
'ROD "Relative Object Design"
'ROP "Receiver Output Peak Check"
'RSP "Related Snap Pattern"
'RSPF "Reduced Standard Parasitic Format"
'RTL "Register Transfer Logic"
'ROT "Rule of Thumb"
'RRU "Repair Register Unit"
'SAI "SoC Architecture Information"
'SAIF "Switching Activity Interchange Format"
'SCBE "Substrate current induced body effect"
'SDC "Standard Design Constraints"
'SDF "Standard Delay Format"
'SDL "Schematic Driven Layout"
'SDP "Structured Data Paths"
'SDR "Simulation driven routing"
'SE "Simulation Environment"
'SFF "Scan Flip-Flop"
'SGE "Sun Grid Engine"
'SHDB "Stylus Hierarchical Database"
'SHE "Self Heating Effects"
'SHM "Simulation History Manager"
'SI "Signal Integrity"
'Si2 "Silicon Integration Initiative"
'SIU "Sequence Iterator Unit"
'SIS "Single Input Switching"
'SKILL "Silicon Compiler Interface Language"
'SMART "Signal integrity, Manufacturing Awareness, Routability, and Timing"
'SMSC "Single Mode Single Corner"
'SNA "Substrate Noise Analysis"
'SNR "Signal to Noise Ratio"
'SOA "Safe Operating Area"
'SOAC "Safe Operating Area Check"
'SoC "System on a Chip"
'SOCV "Statistical On-chip Variation"
'SOI "Silicon-on-Insulator"
'SPD "Symbolic Placement of Devices"
'SPF "Standard Parasitic Format"
'SPICE "Simulation Program with Integrated Circuit Emphasis"
'SRC "Schematic Rule Checker"
'SSS "Simulation Snapshot"
'SST2 "Stanford Sentiment Treebank V2"
'SSTA "Statistical Static Timing Analysis"
'SSV "Silicon Signoff and Verification"
'STA "Static Timing Analysis"
'STI "Shallow Trench Isolation"
'SV "System Verilog"
'SVP "Silicon Virtual Prototype"
'SVS "Schematic Versus Schematic"
'TPR "Tanner Place and Route"
'TAT "Turnaround Time"
'TCF "Toggle Count Format"
'Tcl "Tool Command Language"
'TDDB "Time Dependent Dielectric Breakdown"
'TNS "Total Negative Slack"
'TPA "Track Pattern Assistant"
'TRP "Transfer Property Control"
'TSG "Text-to-Symbol Generator"
'TSV "Through-Silicon Via"
'TW "Timing Window"
'UCM "Universal Connect Modules"
'UCN "Update Components and Nets"
'ULP "Update Layout Parameters"
'UNL "Unified Netlister"
'UPF "Unified Power Format"
'USP "Update Schematic Parameters"
'VCD "Value Change Dump"
'VCO "Voltage Controlled Oscillator"
'VCP "Virtuoso Custom Digital Placer"
'VDI "Virtuoso Digital Implementation"
'VDR "Voltage-Dependent Rules"
'VDSP "Virtuoso Digital Signoff for Power"
'VDST "Virtuoso Digital Signoff for Timing"
'VIPVS "Virtuoso Integrated Physical Verification System"
'VFP "Virtuoso Floorplanner"
'VHDL "Very High Speed Integrated Circuit HDL"
'ViVA "Virtuoso Visualization and Analysis"
'VLM "Virtuoso Layout Optimize"
'VLS "Virtuoso Layout Suite"
'VLS_GXL "Virtuoso Layout Suite GXL"
'VLS_L "Virtuoso Layout Suite L"
'VLS_XL "Virtuoso Layout Suite XL"
'VMF "Virtual Metal Fill"
'VSE "Virtuoso Schematic Editor"
'VSR "Virtuoso Space-based Router"
'VVO "Virtuoso Variation Option"
'WDF "Workshare Compare Delta File"
'WDU "Whitebox Design Unit"
'WEE "Wire-Edge Enlargement"
'WLM "Wire-Load Model"
'WNS "Worst Negative Slack"
'WPE "Well Proximity Effect"
'WSP "Width Spacing Pattern"))