Electronic Design Automation (EDA) acronyms with a special focus on Cadence software.
- Analog Auto Placer (AAP)
- Advanced Boolean Engine (ABE)
- Activity-Driven Restructuring (ADR)
- Advanced On-chip Variation (AOCV)
- Analog Design Environment (ADE)
- Analog Expression Language (AEL)
- Automatically-inserted Connect Module (AICM)
- Algorithm Memory Unit (AMU)
- Analog-Mixed-Signal (AMS)
- AMS Designer (AMSD)
- Analog on Top (AoT)
- AND-OR-invert (AOI)
- Accelerated Parallel Simulation (APS)
- Automatic Test Pattern Generation (ATPG)
- AMS Virtuoso Use Model (AVUM)
- Applied Wave Research (AWR)
- AMS Xcelium Use Model (AXUM)
- Application Programming Interface (API)
- Arithmetic Logic Unit (ALU)
- Application-Specific Integrated Circuit (ASIC)
- Automatic Symbol Generator (ASG)
- Best-Case/Worst-Case (BCWC)
- Block-based Discipline Resolution (BDR)
- Blackbox Design Unit (BDU)
- Back End of Line (BEOL)
- Bit Error Rate (BER)
- Ball Grid Array (BGA)
- Bipolar Complementary Metal Oxide Silicon (BiCMOS)
- Berkeley Short-Channel IGFET Model (BSIM)
- Built-in Self Test (BIST)
- Computer Aided Design (CAD)
- Constraint Aware Editing (CAE)
- Cadence Academic Network (CAN)
- Check Against Source (CAS)
- Channel Connected Component (CCC)
- Conformal Constraints Designer (CCD)
- Clock Constraint File (CCF)
- Common Command Language (CCL)
- Clock Concurrent Optimization (CCOpt)
- Cadence Change Request (CCR)
- Composite Current Source (CCS)
- Cadence Doc Assistant (CDA)
- Clock Domain Crossing (CDC)
- Component Description Format (CDF)
- Circuit Description Language (CDL)
- Charge Device Model (CDM)
- Cadence Database API (CDBA)
- Cadence Design Systems (CDS)
- Caltech Intermediate Format (CIF)
- CDF Expression Language (CEL)
- Computational Fluid Dynamics (CFD)
- Clock-gating integrated cell (CGIC)
- Command Interpreter Window (CIW)
- Compile Module Interface (CMI)
- Concurrent Multi-Mode Multi Corner (CMMMC)
- Compile Module Interface (CMI)
- Complementary Metal Oxide Silicon (CMOS)
- Chemical Mechanical Polishing (CMP)
- Common Power Format (CPF)
- Cadence Database (CDB)
- Concurrent Layout Editing (CLE)
- Compact Modeling Counsel (CMC)
- Cadence Placement Guidance (CPG)
- Configure Physical Hierarchy (CPH)
- Clock Path Pessimism Removal (CPPR)
- Connect Modules (CM)
- Connect Rules (CR)
- Clock Reconvergence Pessimism Removal (CRPR)
- Carry-Save Adder (CSA)
- Cadence Space-based Router (CSR)
- Clock Tree Debugger (CTD)
- Clock Tree Synthesis (CTS)
- Constraint Validation (CV)
- Common User Interface (CVD)
- Database Units (DBU)
- Data Compare Unit (DCU)
- Define Device Correspondence (DDC)
- Determinant Decision Diagram (DDD)
- Design Data Procedural Interface (DDPI)
- Design Framework II (DFII)
- Design for Manufacturability (DFM)
- Design for Test (DFT)
- Detailed Standard Parasitic Format (DSPF)
- Drain-induced barrier lowering (DIBL)
- Drain-induced threshold shift (DITS)
- Differential Nonlinearity (DNL)
- Distributed Multi-Mode Multi Corner (DMMMC)
- Double Metal Insulator Metal (DMIM)
- Digital Centric Mixed-Signal (DMS)
- Digital on Top (DoT)
- Dual Port Object (DPO)
- Disembodied Property List (DPL)
- Driver-Receiver Segregation (DRS)
- Double Patterning Technology (DPT)
- Discipline Resolution (DR)
- Design Rule Check (DRC)
- Design Rule Driven (DRD)
- Dynamic Rule Filtering (DRF)
- Device Recognition Layer (DRL)
- Design Rule Manual (DRM)
- Design Rule Violation (DRV)
- Detaild Standard Parasitic Format (DSTA)
- Deep-Submicron (DSM)
- Distributed Static Timing Analysis (DSM)
- Device under Test (DUT)
- Dynamic Voltage Supply (DVS)
- Error-Correcting Codes (ECC)
- Early Clock Flow (ECF)
- Engineering Change Order (ECO)
- Effective Current Source Model (ECSM)
- Electronic Design Automation (EDA)
- Electronic Design Interchange Format (EDIF)
- Electromigration (EM)
- Embedded Module Hierarchy (EMH)
- Edit In Place (EIP)
- Effective Instance Voltage (EIV)
- Electromigration and IR-Drop (EMIR)
- Effective Number of Bits (ENOB)
- Equivalent Oxide Thickness (EOT)
- Early Rail Analysis (ERA)
- Electrical Rule Check (ERC)
- Electrostatic Discharge (ESD)
- Effective Series Resistance (ESR)
- Edge Triggered Latch (ETL)
- Extracted Timing Model (ETM)
- Field-Effect Transistor (FET)
- Forward Body Bias (FBB)
- Fuse Control Unit (FCU)
- Front End of Line (FEOL)
- Flip-Flop (FF)
- Fluid Guard Ring (FGR)
- Fowler-Nordheim (FN)
- Flat Netlister (FNL)
- Field-Programmable Gate Array (FPGA)
- Fast Signal Database (FSDB)
- Finite State Machine (FSM)
- Full Timing Model (FTM)
- Graph-Based Analysis (GBA)
- Generic Design Management (GDM)
- Graphical Design Station II (GDSII)
- Generate From Source (GFS)
- Gates-All-Around FET (GAA FET)
- Gate Induced Drain Leakage (GIDL)
- Gate Induced Source Leakage (GISL)
- Graphical LVS Debugger (GLD)
- Gate-Level Simulation (GLS)
- Grid Pattern Editor (GPE)
- Generate Physical Hierarchy (GPH)
- Grid Pattern Mapping (GPM)
- Generate Selected From Source (GSFS)
- Global Timing Debug (GTD)
- Harmonic
Balance(HB) - Hetero-Junction Bipolar Transistor (HBT)
- Human-Body Model (HBM)
- Hot Carrier Injection (HCI)
- Hardware Description Language (HDL)
- Hierarchy Editor (HED)
- Hierarchical Metal Fill Database Flow (HMF)
- Hierarchical Netlister (HNL)
- High Performance Blocking (HPB)
- Hierarchical Extraction (HRCX)
- Hierarchical Pattern Matching (HPM)
- I/O Buffer Information Specification (IBIS)
- Integrated Circuit Advanced Node and Advanced Methodologies (ICADVM)
- Internet Learning Series (ILS)
- Instructor-Led Training (ILT)
- Integration Constraint Editor (ICE)
- Interconnect Technology (ICT)
- IC Remote Processes (ICRP)
- International Technology Roadmap for Semiconductors (ITRS)
- Interface Element (IE)
- Insulated-Gate Field-Effect Transistor (IGFET)
- Inter-Layer Dielectric (ILD)
- Interface Logic Models (ILM)
- Interprocess Communication (IPC)
- Incremental Optimization (IOPT)
- Interactive Simulation Environment (ISE)
- Intellectual Property (IP)
- Interactive Short Locator (ISL)
- Kirchhoff’s Current Law (KCL)
- Kirchhoff’s Voltage Law (KVL)
- Lightly Doped Drain (LDD)
- Layout-Dependent Effects (LDE)
- Low-Discrepancy Sequence (LDS)
- Logic Equivalence Checking (LEC)
- Library Exchange Format (LEF)
- Land Grid Array (LGA)
- Latin Hypercube Sampling (LHS)
- Local Oxidation of Silicon (LOCOS)
- Low Pass Filter (LPF)
- Layer-Purpose Pair (LPP)
- Least Resistive Path (LRP)
- Large-Scale Cloud Simulation (LSCS)
- Load Sharing Facility (LSF)
- Large-Signal
S-ParameterParameters~(LSSP) - Local Truncation Error (LTE)
- Liberty Variation Format (LVF)
- Layout Versus Layout (LVL)
- Layout Versus Schematic (LVS)
- Multibit Cell Inference (MBCI)
- Monte Carlo (MC)
- Multicycle Path (MCP)
- Multi Input Switching (MIS)
- Metal-Insulator Semiconductor FET (MISFET)
- Metal-Oxide Semiconductor FET (MOSFET)
- Measurement Description Language (MDL)
- Middle End of Line (MEOL)
- Metal Insulator Metal (MIM)
- Machine Model (MM)
- Multi-Mode Multi-Corner (MMMC)
- Module Generator (MODGEN)
- Multiple Process Corner (MPC)
- Multipart Path (MPP)
- Multi-Patterning Technology (MPT)
- Multi-Project Wafer (MPW)
- Multiple Supply Voltage (MSV)
- Multi-Technology Simulation (MTS)
- NanoRoute High Frequency Router (NRHF)
- National Instruments (NI)
- Negative Bias Temperature Instability (NTBI)
- Netlist property (NLP)
- Non-linear Delay Model (NLDM)
- Nonquasi-static (NQS)
- Near-Threshold (NT)
- Open Access (OA)
- OR-AND-invert (OAI)
- Open Artwork System Interchange Standard (OASIS)
- One-Button-Checker (OBC)
- On-Chip Variation (OCV)
- Out-Of-Module Reference (OOMR)
- Out-of-Context Probing (OOP)
- Optical Proximity Correction (OPC)
- On-Product Clock Generation (OPCG)
- Open Simulation System for Netlisting (OSSN)
- Process Antenna Effect (PAE)
- Protected Backgate (PBKG)
- Process Design Kit (PDK)
- Parasitic Extraction (PEX)
- Polysilicon Insulator Polysilicon (PIP)
- Programmable Logic Array (PLA)
- Physical Layout Estimation (PLE)
- Performance, Power and Area (PPA)
- Place and Route (PR)
- Process Rule Overrides (PRO)
- Path-Based Analysis (PBA)
- Pseudo-Random Bit Sequence (PBRS)
- Process-Based Save/Restart (PBSR)
- PCell Designer (PCD)
- Phase Detector (PD)
- Power-Delay Product (PDP)
- Partial Element Equivalent Circuit (PEEC)
- Programmable Electrical Rule Check (PERC)
- Plastic Leadless Chip Carrier (PLCC)
- Phase Locked Loop (PLL)
- Parameter Storage Format (PSF)
- Power Supply Network (PSN)
- Periodic Steady State (PSS)
- Programmable Memory Built-In Self-Test (PMBIST)
- Power Test Access Mechanism (PTAM)
- Physical Verification Language (PVL)
- Physical Verification Solution (PVS)
- Process, Voltage and Temperature (PVT)
- Quality of Results (QOR)
- Quantus Extraction Solution (QRC)
- Rapid Adoption Kit (RAK)
- Rapid Analog Prototype (RAP)
- Redundancy Analysis Unit (RAU)
- Receiver Input Peak Check (RIP)
- Real Number Modeling (RNM)
- Relative Object Design (ROD)
- Receiver Output Peak Check (ROP)
- Related Snap Pattern (RSP)
- Reduced Standard Parasitic Format (RSPF)
- Register Transfer Logic (RTL)
- Rule of Thumb (ROT)
- Repair Register Unit (RRU)
- SoC Architecture Information (SAI)
- Switching Activity Interchange Format (SAIF)
- Substrate current induced body effect (SCBE)
- Standard Design Constraints (SDC)
- Standard Delay Format (SDF)
- Schematic Driven Layout (SDL)
- Structured Data Paths (SDP)
- Simulation driven routing (SDR)
- Simulation Environment (SE)
- Scan Flip-Flop (SFF)
- Sun Grid Engine (SGE)
- Stylus Hierarchical Database (SHDB)
- Self Heating Effects (SHE)
- Simulation History Manager (SHM)
- Signal Integrity (SI)
- Silicon Integration Initiative (Si2)
- Sequence Iterator Unit (SIU)
- Single Input Switching (SIS)
- Silicon Compiler Interface Language (SKILL)
- Signal integrity, Manufacturing Awareness, Routability, and Timing (SMART)
- Single Mode Single Corner (SMSC)
- Substrate Noise Analysis (SNA)
- Signal to Noise Ratio (SNR)
- Safe Operating Area (SOA)
- Safe Operating Area Check (SOAC)
- System on a Chip (SoC)
- Statistical On-chip Variation (SOCV)
- Silicon-on-Insulator (SOI)
- Symbolic Placement of Devices (SPD)
- Standard Parasitic Format (SPF)
- Simulation Program with Integrated Circuit Emphasis (SPICE)
- Schematic Rule Checker (SRC)
- Simulation Snapshot (SSS)
- Stanford Sentiment Treebank V2 (SST2)
- Statistical Static Timing Analysis (SSTA)
- Silicon Signoff and Verification (SSV)
- Static Timing Analysis (STA)
- Shallow Trench Isolation (STI)
- System Verilog (SV)
- Silicon Virtual Prototype (SVP)
- Schematic Versus Schematic (SVS)
- Tanner Place and Route (TPR)
- Turnaround Time (TAT)
- Toggle Count Format (TCF)
- Tool Command Language (Tcl)
- Time Dependent Dielectric Breakdown (TDDB)
- Total Negative Slack (TNS)
- Track Pattern Assistant (TPA)
- Transfer Property Control (TRP)
- Text-to-Symbol Generator (TSG)
- Through-Silicon Via (TSV)
- Timing Window (TW)
- Universal Connect Modules (UCM)
- Update Components and Nets (UCN)
- Update Layout Parameters (ULP)
- Unified Netlister (UNL)
- Unified Power Format (UPF)
- Update Schematic Parameters (USP)
- Value Change Dump (VCD)
- Voltage Controlled Oscillator (VCO)
- Virtuoso Custom Digital Placer (VCP)
- Virtuoso Digital Implementation (VDI)
- Voltage-Dependent Rules (VDR)
- Virtuoso Digital Signoff for Power (VDSP)
- Virtuoso Digital Signoff for Timing (VDST)
- Virtuoso Integrated Physical Verification System (VIPVS)
- Virtuoso Floorplanner (VFP)
- Very High Speed Integrated Circuit HDL (VHDL)
- Virtuoso Visualization and Analysis (ViVA)
- Virtuoso Layout Optimize (VLM)
- Virtuoso Layout Suite (VLS)
- Virtuoso Layout Suite GXL (VLS GXL)
- Virtuoso Layout Suite L (VLS L)
- Virtuoso Layout Suite XL (VLS XL)
- Virtual Metal Fill (VMF)
- Virtuoso Schematic Editor (VSE)
- Virtuoso Space-based Router (VSR)
- Virtuoso Variation Option (VVO)
- Workshare Compare Delta File (WDF)
- Whitebox Design Unit (WDU)
- Wire-Edge Enlargement (WEE)
- Wire-Load Model (WLM)
- Worst Negative Slack (WNS)
- Well Proximity Effect (WPE)
- Width Spacing Pattern (WSP)