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nietzhuang/README.md

https://github.com/nietzhuang

Welcome my friends 👋 !!

  • I'm Jyun-Siou Huang (黃俊修), you can call me Nietz (I named it 'cause I'm into existentialism).
  • I research Hardware accelerators on AI/ML field, which involve many, such as ASIC/FPGA hardware implementation, hardware modelling, workload scheduling, and etc. You can see my interested papers (here)
  • Currrently, I'm a PhD student at National Tsing Hua University, Taiwan. Welcome to contact me if you have the same research interests with me.
  • Besides, I play the violin, enjoying Classics and Jazz in my leisure time. If you wish, follow my social media and make friends.

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  1. Cycle-accurate-Eyeriss-model Cycle-accurate-Eyeriss-model Public

    A scalable Eyeriss model in SystemC.

    C++ 23 3

  2. RISC-V-SoC-Design RISC-V-SoC-Design Public

    Single RISC-V CPU attached on AMBA AHB with Instruction and Data memories.

    SystemVerilog 11

  3. AIML-random-resources AIML-random-resources Public

    This repository collects lots of useful resources sharing from AI/ML Community discord server.

    9

  4. 2019-CIC-Contest---Image-Convolutional-Circuit-Design 2019-CIC-Contest---Image-Convolutional-Circuit-Design Public

    2019 CIC contest preliminary topic

    Verilog 7