fix(hal/imx8mn): fix for uSDHC driver, sending sd-cmds now works

nihalpasham · May 13, 2023 · 8437fd2 · 8437fd2
1 parent 6dcad2e
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diff --git a/boards/bootloaders/imx8mn/debug.md b/boards/bootloaders/imx8mn/debug.md
@@ -8,29 +8,46 @@ Port /dev/tty.usbserial-1101, 11:47:54
 
 Press Meta-Z for help on special keys
 
-[    0.000249] imx8mn-rs version 0.1.0
-[    0.003708] Booting on: i.MX 8M Nano EVK
-[    0.007704] Current privilege level: EL3
-[    0.011687] Exception handling state:
-[    0.015486]       Debug:  Masked
-[    0.018770]       SError: Unmasked
-[    0.022237]       IRQ:    Masked
-[    0.025530]       FIQ:    Masked
-[    0.028797] Drivers loaded:
-[    0.031522]       1. i.MX8M Uart2
-[    0.034975] Chars written: 382
-[    0.038089] uSDHC2 has support for 1.8v, 3.0v, 3.3v ...
-[    0.043339] Sd host circuit reset in 4us
-[    0.047362] Sd clock stablized in 38us
-[    0.051125] Prescaler = 64, Divisor = 16, Freq Set = 390625
-[    0.057011] Sd: sending command, CMD_NAME: "GO_IDLE_STATE", CMD_CODE: 0x00000000, CMD_ARG: 0x00000000
-[    0.069780] Sd: sending command, CMD_NAME: "SEND_IF_COND", CMD_CODE: 0x081a0000, CMD_ARG: 0x000001aa
-[    0.084405] Error: we got a response for the last cmd but it contains errors, decode contents of interrupt status register for details
-               VendSpec: 0x20007879, SysCtrl: 0x008f20ff, ProtCtrl: 0x08800020, PresentStatus: 0xf0058088, intStatus: 0x000c8001, Resp0: 0x00000000, Resp1: 0x00000000,
-Resp2: 0x00000000, Resp3: 0x00000000, CC_bit set in 4084us
+[    0.000005] imx8mn-rs version 0.1.0
+[    0.003584] Booting on: i.MX 8M Nano EVK
+[    0.007607] Current privilege level: EL3
+[    0.011545] Exception handling state:
+[    0.015345]       Debug:  Masked
+[    0.018591]       SError: Unmasked
+[    0.022112]       IRQ:    Masked
+[    0.025395]       FIQ:    Masked
+[    0.028603] Drivers loaded:
+[    0.031523]       1. i.MX8M Uart2
+[    0.034965] Chars written: 382
+[    0.037976] uSDHC2 supports 1.8v, 3.0v, 3.3v ...
+[    0.042765] Sd clock stablized in 38us
+[    0.046555] Prescaler = 64, Divisor = 16, Freq = 390625 Hz
+[    0.052420] Sd: sending command, CMD_NAME: "GO_IDLE_STATE", CMD_CODE: 0x00000000, CMD_ARG: 0x00000000
+[    0.065373] Sd: sending command, CMD_NAME: "SEND_IF_COND", CMD_CODE: 0x081a0000, CMD_ARG: 0x000001aa
+[    0.076527] Sd: sending command, CMD_NAME: "APP_CMD", CMD_CODE: 0x371a0000, CMD_ARG: 0x00000000
+[    0.087369] Sd: sending command, CMD_NAME: "APP_SEND_OP_COND", CMD_CODE: 0x29020000, CMD_ARG: 0x50ff8000
+[    0.499191] Sd: sending command, CMD_NAME: "APP_CMD", CMD_CODE: 0x371a0000, CMD_ARG: 0x00000000
+[    0.509984] Sd: sending command, CMD_NAME: "APP_SEND_OP_COND", CMD_CODE: 0x29020000, CMD_ARG: 0x50ff8000
+[    0.521794] Sd: sending command, CMD_NAME: "ALL_SEND_CID", CMD_CODE: 0x02090000, CMD_ARG: 0x00000000
+[    0.533471] Sd: sending command, CMD_NAME: "SEND_REL_ADDR", CMD_CODE: 0x03020000, CMD_ARG: 0x00000000
+[    0.544576] Sd: sending command, CMD_NAME: "SEND_CSD", CMD_CODE: 0x09010000, CMD_ARG: 0x00010000
+[    0.555735] CSD Contents : 00 40 0e 00 32 5b 59 00 003b 83 7f 80 0a 40 00
+[    0.562789] cemmc_structure=1, spec_vers=0, taac=0x0E, nsac=0x00, tran_speed=0x32,ccc=0x05B5, read_bl_len=0x09, read_bl_partial=0b, write_blk_misalign=0b,read_blk_misalign=0b, dsr_imp=0b, sector_size =0x7F, erase_blk_en=1b
+[    0.583485] CSD 2.0: ver2_c_size = 0x3BFF, card capacity: 7987527680 bytes or 7.99GiB
+[    0.591571] wp_grp_size=0x0000000b, wp_grp_enable=0b, default_ecc=00b, r2w_factor=010b, write_bl_len=0x09, write_bl_partial=0b, file_format_grp=0, copy=0b, perm_write_protect=0b, tmp_write_protect=0b, file_format=0b ecc=00b
+[    0.612260] Sd clock stablized in 0us
+[    0.616093] Prescaler = 1, Divisor = 8, Freq = 50000000 Hz
+[    0.621697] Sd: sending command, CMD_NAME: "CARD_SELECT", CMD_CODE: 0x07030000, CMD_ARG: 0x00010000
+[    0.632286] Sd: sending command, CMD_NAME: "APP_CMD_RCA", CMD_CODE: 0x37020000, CMD_ARG: 0x00010000
+[    0.642606] Sd: sending command, CMD_NAME: "SEND_SCR", CMD_CODE: 0x333a0000, CMD_ARG: 0x00000000
+[    0.653013] SCR bus width: WIDTH_1_4
+[    0.656649] Sd: sending command, CMD_NAME: "APP_CMD_RCA", CMD_CODE: 0x37020000, CMD_ARG: 0x00010000
+[    0.667078] Sd: sending command, CMD_NAME: "SET_BUS_WIDTH", CMD_CODE: 0x06020000, CMD_ARG: 0x00010002
+[    0.677648] Sd Bus width set to 4
+[    0.680970] Sd: sending command, CMD_NAME: "SET_BLOCKLEN", CMD_CODE: 0x10000000, CMD_ARG: 0x00000200
+[    0.691651] Sd Card: Type 2 HC, 7617Mb, mfr_id: 150, 'DE:SD', r2.0, mfr_date: 1/2021, serial: 0x424f0218, RCA: 0x0001
+[    0.703020] uSDHC driver initialized
+[    0.706679]
 
-[    0.118136] SdError: Send interface condition command (CMD8) returned an error
-[    0.125688] failed to initialize
-[    0.128972]
-[    0.130618]  ... wait forever
+[    0.708156]  ... wait forever
 ```
diff --git a/boards/bootloaders/imx8mn/src/boot.rs b/boards/bootloaders/imx8mn/src/boot.rs
@@ -6,7 +6,7 @@ use crate::kernel_init;
 use crate::{
     clocks, exception, memory,
     mux::{uart2grp::uart2_mux_mmio_set, usdhc2grp::usdhc2_mux_mmio_set},
-    start_system_counter, sys_clocks_init,
+    start_system_counter,
 };
 
 // Assembly counterpart to this file.
@@ -26,8 +26,6 @@ pub unsafe extern "C" fn _start_rust() -> ! {
     clocks::scntrclk::enable_sctr();
     // start the system counter, this allows us to access ARM's architectural counter - CNTPCT_EL0
     start_system_counter();
-    // initialize system clocks
-    sys_clocks_init();
     // enable Uart and uSDHC clock 
     clocks::uartclks::enable_uart_clk(1);
     clocks::usdhcclks::enable_usdhc_clk(2);

diff --git a/boards/bootloaders/imx8mn/src/main.rs b/boards/bootloaders/imx8mn/src/main.rs
@@ -12,7 +12,7 @@ use rustBoot_hal::nxp::imx8mn::bsp::{
     clocks,
     drivers::{
         common::interface::DriverManager,
-        driver_manager::{driver_manager, start_system_counter, sys_clocks_init},
+        driver_manager::{driver_manager, start_system_counter},
     },
     global, mux,
 };
@@ -66,7 +66,7 @@ fn kernel_main() -> ! {
 
     // init uSDHC
     match SDHC2.init_usdhc() {
-        SdResult::SdOk => info!("uSDHC driver initialized"),
+        SdResult::SdOk => info!("uSDHC driver initialized..."),
         _ => info!("failed to initialize"),
     }
 

diff --git a/boards/hal/src/nxp/imx8mn/bsp/clocks/analog.rs b/boards/hal/src/nxp/imx8mn/bsp/clocks/analog.rs
@@ -1,3 +1,5 @@
+//! PLL configuration - TODO - implementation not ready yet
+
 use tock_registers::interfaces::ReadWriteable;
 use tock_registers::{
     interfaces::{Readable, Writeable},
@@ -351,6 +353,7 @@ impl CCMAnalog {
                 + SYS_PLL2_GEN_CTRL::PLL_DIV20_CLKE::SET,
         )
     }
+    /// TODO: implementation not complete. Still needs to be tested
     pub fn pll_configure(&self, pll: PllClocks, freq: u32) {
         let pll_clke_masks = INTPLL_CLKE_MASK;
         // Bypass clock and set lock to pll output lock
@@ -434,7 +437,7 @@ impl CCMAnalog {
             _ => {}
         }
     }
-
+    /// TODO: implementation not complete. Still needs to be tested
     /// Configure system Plls and set clock-gates, root-clocks for GIC, DRAM, NAND, WDG etc.
     pub fn clock_init(&self) {
         self.set_pll1_outputs();

diff --git a/boards/hal/src/nxp/imx8mn/bsp/drivers/gpio.rs b/boards/hal/src/nxp/imx8mn/bsp/drivers/gpio.rs
@@ -184,14 +184,13 @@ impl GpioInner {
 
     /// Set GPIO pin
     fn set_gpio_pin(&mut self, pin: u8, val: bool) {
-        // Set pin-direction to output
-        self.registers
-            .GPIO_GDIR
-            .modify(GPIO_GDIR::PIN_DIR.val(1 << pin));
-
         // set or clear DR bit for corresponding pin
         match val {
             true => {
+                // Set pin-direction to output
+                self.registers
+                    .GPIO_GDIR
+                    .modify(GPIO_GDIR::PIN_DIR.val(1 << pin));
                 self.registers.GPIO_DR.modify(GPIO_DR::DR.val(1 << pin));
             }
             false => {
@@ -224,17 +223,17 @@ impl Gpio {
             inner: NullLock::new(GpioInner::new(mmio_start_addr)),
         }
     }
-    /// Sets the supplied Gpio pin's state to output
+    /// Sets the supplied Gpio pin's direction and state to output
     pub fn set_pin(&self, pin: u8) {
-        self.inner.lock(|gpio | gpio.set_gpio_pin(pin, true));
+        self.inner.lock(|gpio| gpio.set_gpio_pin(pin, true));
     }
     /// Clears the supplied Gpio pin's output-mode status
     pub fn clear_pin(&self, pin: u8) {
-        self.inner.lock(|gpio | gpio.set_gpio_pin(pin, false));
+        self.inner.lock(|gpio| gpio.set_gpio_pin(pin, false));
     }
     /// Reads the the supplied Gpio pin's state.
     pub fn read_pin(&self, pin: u8) -> u8 {
-        let res = self.inner.lock(|gpio | gpio.get_gpio_pin(pin));
+        let res = self.inner.lock(|gpio| gpio.get_gpio_pin(pin));
         res
     }
 }
@@ -247,4 +246,3 @@ impl super::common::interface::DeviceDriver for Gpio {
         "i.MX 8M Nano Gpio"
     }
 }
-