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Add pass for lowering to accel ukernels.
Add lit test and fix build. Fixes to LowerToAccelUKernelPass Tweaks to LowerToAccelUKernelsPass. Add AccelMatmulExpert pass pipeline Apply clang-format to new C++ files. (#3) - Apply clangformat. use 'accel' identifier Use parameter struct calling convention Tweaks to KernelDispatch and AccelMatmulExpert pipeline Co-authored-by: Sungsoon Cho <[email protected]>
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142 changes: 142 additions & 0 deletions
142
compiler/src/iree/compiler/Codegen/LLVMCPU/LLVMCPULowerToAccelUKernels.cpp
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| // Copyright 2023 The IREE Authors | ||
| // | ||
| // Licensed under the Apache License v2.0 with LLVM Exceptions. | ||
| // See https://llvm.org/LICENSE.txt for license information. | ||
| // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception | ||
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| #include "iree-dialects/Dialect/LinalgExt/IR/LinalgExtOps.h" | ||
| #include "iree/builtins/ukernel/exported_bits.h" | ||
| #include "iree/compiler/Codegen/Dialect/IREECodegenDialect.h" | ||
| #include "iree/compiler/Codegen/Dialect/IREECodegenOps.h" | ||
| #include "iree/compiler/Codegen/Dialect/UKernelOps.h" | ||
| #include "iree/compiler/Codegen/LLVMCPU/PassDetail.h" | ||
| #include "iree/compiler/Codegen/LLVMCPU/Passes.h" | ||
| #include "mlir/Dialect/Arith/IR/Arith.h" | ||
| #include "mlir/Dialect/Func/IR/FuncOps.h" | ||
| #include "mlir/Dialect/Linalg/IR/Linalg.h" | ||
| #include "mlir/Dialect/Tensor/IR/Tensor.h" | ||
| #include "mlir/IR/Attributes.h" | ||
| #include "mlir/IR/BuiltinAttributes.h" | ||
| #include "mlir/IR/BuiltinTypes.h" | ||
| #include "mlir/IR/MLIRContext.h" | ||
| #include "mlir/IR/Matchers.h" | ||
| #include "mlir/IR/TypeRange.h" | ||
| #include "mlir/Transforms/GreedyPatternRewriteDriver.h" | ||
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| namespace mlir { | ||
| namespace iree_compiler { | ||
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| namespace { | ||
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| class LLVMCPULowerToAccelUKernelsPass | ||
| : public LLVMCPULowerToAccelUKernelsBase<LLVMCPULowerToAccelUKernelsPass> { | ||
| public: | ||
| LLVMCPULowerToAccelUKernelsPass() = default; | ||
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| void getDependentDialects(DialectRegistry ®istry) const override { | ||
| registry.insert<IREE::Codegen::IREECodegenDialect>(); | ||
| } | ||
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| void runOnOperation() override; | ||
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| LogicalResult initializeOptions(StringRef options) override { | ||
| if (failed(Pass::initializeOptions(options))) { | ||
| return failure(); | ||
| } | ||
| return success(); | ||
| } | ||
| }; | ||
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| /// Holds a function name and attributes. | ||
| struct FnNameAndDefAttrs { | ||
| std::string name; | ||
| SmallVector<NamedAttribute> defAttrs; | ||
| }; | ||
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| /// Returns the function name and attributes to use for a ukernel with given | ||
| /// `ukernelName` on the target described by `targetAttr`. | ||
| static FnNameAndDefAttrs | ||
| getFnNameAndDefAttrs(const char *ukernelName, RewriterBase &rewriter, | ||
| IREE::HAL::ExecutableTargetAttr targetAttr) { | ||
| FnNameAndDefAttrs result; | ||
| result.name = ukernelName; | ||
| result.defAttrs.emplace_back( | ||
| rewriter.getStringAttr("hal.import.fields"), | ||
| rewriter.getArrayAttr({rewriter.getStringAttr("processor_data"), | ||
| rewriter.getStringAttr("processor_id")})); | ||
| result.defAttrs.emplace_back( | ||
| rewriter.getStringAttr("hal.import.cconv"), | ||
| IREE::HAL::CallingConventionAttr::get( | ||
| rewriter.getContext(), | ||
| IREE::HAL::CallingConvention::ParameterStruct)); | ||
| return result; | ||
| } | ||
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| /// Matches an (linalg.fill -> )? linalg.matmul operation sequence and converts | ||
| /// it into a iree_codegen.ukernel.generic "accel_matmul_f32" operation, that is later lowered | ||
| /// into a call to the microkernel. | ||
| static FailureOr<IREE::Codegen::UKernelOpInterface> | ||
| matchDAGForUKernel(RewriterBase &rewriter, linalg::MatmulOp op) { | ||
| Value lhs = op.getDpsInputOperand(0)->get(); | ||
| Value rhs = op.getDpsInputOperand(1)->get(); | ||
| Value out = op.getDpsInitOperand(0)->get(); | ||
| auto outType = llvm::cast<ShapedType>(out.getType()); | ||
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| Location loc = op.getLoc(); | ||
| Value m = rewriter.create<tensor::DimOp>(loc, lhs, 0); | ||
| Value n = rewriter.create<tensor::DimOp>(loc, rhs, 0); | ||
| Value k = rewriter.create<tensor::DimOp>(loc, rhs, 1); | ||
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| auto targetAttr = IREE::HAL::ExecutableTargetAttr::lookup(op); | ||
| auto fn = getFnNameAndDefAttrs("accel_matmul_f32", rewriter, targetAttr); | ||
| auto genericMicroKernelOp = rewriter.create<IREE::Codegen::UKernelGenericOp>( | ||
| loc, outType, fn.name, ValueRange{lhs, rhs}, out, ValueRange{m, n, k}, | ||
| /*fn_def_attrs=*/rewriter.getDictionaryAttr(fn.defAttrs), | ||
| /*strided_outer_dims=*/rewriter.getIndexAttr(0)); | ||
| return cast<IREE::Codegen::UKernelOpInterface>( | ||
| genericMicroKernelOp.getOperation()); | ||
| } | ||
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| template <typename OpType> | ||
| struct LowerToAccelUKernelPattern : OpRewritePattern<OpType> { | ||
| LowerToAccelUKernelPattern(MLIRContext *context) | ||
| : OpRewritePattern<OpType>(context) {} | ||
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| LogicalResult matchAndRewrite(OpType op, | ||
| PatternRewriter &rewriter) const override { | ||
| FailureOr<IREE::Codegen::UKernelOpInterface> ukernelOp = | ||
| matchDAGForUKernel(rewriter, op); | ||
| if (failed(ukernelOp)) { | ||
| return rewriter.notifyMatchFailure( | ||
| op, "failed to find microkernel op to replace with"); | ||
| } | ||
| rewriter.replaceOp(op, ukernelOp.value()->getResults()); | ||
| return success(); | ||
| } | ||
| }; | ||
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| void LLVMCPULowerToAccelUKernelsPass::runOnOperation() { | ||
| MLIRContext *context = &getContext(); | ||
| RewritePatternSet patterns(context); | ||
| // Enabling a lowering of an op to a microkernel is a trade-off between the | ||
| // potential performance advantage of a microkernel over pure code generation | ||
| // for that op, and the potential benefits of fusions. Indeed, once an op | ||
| // lowered into a microkernel, it will never be fused at any MLIR level. | ||
| // Since microkernels are linked as bitcode, they will still undergo LTO-like | ||
| // optimization in their calling contexts, but we shouldn't expect this to | ||
| // achieve similar results as fusing structured ops. | ||
| patterns.insert<LowerToAccelUKernelPattern<linalg::MatmulOp>>(context); | ||
| if (failed( | ||
| applyPatternsAndFoldGreedily(getOperation(), std::move(patterns)))) { | ||
| return signalPassFailure(); | ||
| } | ||
| } | ||
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| } // namespace | ||
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| std::unique_ptr<OperationPass<>> createLLVMCPULowerToAccelUKernelsPass() { | ||
| return std::make_unique<LLVMCPULowerToAccelUKernelsPass>(); | ||
| } | ||
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| } // namespace iree_compiler | ||
| } // namespace mlir |
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23 changes: 23 additions & 0 deletions
23
compiler/src/iree/compiler/Codegen/LLVMCPU/test/lower_to_accel_ukernel_ops.mlir
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| Original file line number | Diff line number | Diff line change |
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| @@ -0,0 +1,23 @@ | ||
| // RUN: iree-opt --pass-pipeline="builtin.module(func.func(iree-llvmcpu-lower-to-accel-ukernels,cse,canonicalize))" %s | FileCheck %s | ||
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| func.func @matmul_f32f32f32(%arg0 : tensor<?x?xf32>, %arg1 : tensor<?x?xf32>, %arg2 : tensor<?x?xf32>) -> tensor<?x?xf32> { | ||
| %0 = linalg.matmul ins(%arg0, %arg1 : tensor<?x?xf32>, tensor<?x?xf32>) | ||
| outs(%arg2 : tensor<?x?xf32>) -> tensor<?x?xf32> | ||
| return %0 : tensor<?x?xf32> | ||
| } | ||
| // CHECK: func @matmul_f32f32f32( | ||
| // CHECK-SAME: %[[ARG0:[a-zA-Z0-9]+]]: tensor<?x?xf32> | ||
| // CHECK-SAME: %[[ARG1:[a-zA-Z0-9]+]]: tensor<?x?xf32> | ||
| // CHECK-SAME: %[[ARG2:[a-zA-Z0-9]+]]: tensor<?x?xf32> | ||
| // CHECK-DAG: %[[C0:.+]] = arith.constant 0 | ||
| // CHECK-DAG: %[[C1:.+]] = arith.constant 1 | ||
| // CHECK-DAG: %[[M:.+]] = tensor.dim %[[ARG0]], %[[C0]] | ||
| // CHECK-DAG: %[[N:.+]] = tensor.dim %[[ARG1]], %[[C0]] | ||
| // CHECK-DAG: %[[K:.+]] = tensor.dim %[[ARG1]], %[[C1]] | ||
| // CHECK: %[[MICRO_KERNEL:.+]] = iree_codegen.ukernel.generic "aie_matmul_f32" | ||
| // CHECK-SAME: ins(%[[ARG0]], %[[ARG1]] : | ||
| // CHECK-SAME: outs(%[[ARG2]] : | ||
| // CHECK-SAME: (%[[M]], %[[N]], %[[K]] : | ||
| // CHECK-DAG: "processor_id" | ||
| // CHECK-DAG: "processor_data" | ||
| // CHECK: return %[[MICRO_KERNEL]] |
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