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ombhilare999/README.md

Omkar Bhilare

(Digital Design and Verification Enthusiast)

I am a first-year MASc (Master of Applied Science) student at the University of Toronto, working under the guidance of Professor Jason Anderson. CGRAs are a type of reconfigurable device known for their potential to deliver greater performance gains compared to other reconfigurable hardware, such as FPGAs. My current research focuses on developing various CAD mapping algorithms for CGRAs to enable efficient application execution and maximize hardware performance.

Before starting my master's, I worked as a Silicon Design Engineer at AMD in India. During my undergraduate studies in Electronics, I interned with Prof. Paolo Ienne at EPFL for the Dynamatic project, Prof. Kamakoti at IIT Madras on the Shakti project, and participated in the Google Summer of Code with BeagleBoard.org for the BeagleWire project. I am always open to research opportunities in Computer Architecture, Reconfigurable Computing, and RTL Design & Verification. Feel free to connect with me if you would like to discuss any ideas or any of my previous work.

In my free time, I like to play cricket, chess, and watch movies.

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  1. BeagleWire BeagleWire Public

    Forked from BeagleWire/BeagleWire

    This repository contains software for BeagleWire. Docs of BeagleWire: https://beaglewire.github.io/

    Verilog 1

  2. SRA-VJTI/sra-board-hardware-design SRA-VJTI/sra-board-hardware-design Public

    ESP32-based Development Board for Robotics and Embedded Applications

    69 24

  3. riscv-core riscv-core Public

    A customized RISCV core made using verilog

    Verilog 19 3

  4. 8-bit-computer 8-bit-computer Public

    8 bit computer using sap logic

    Python 6

  5. vga-interface-with-TANG-PRIMER-FPGA vga-interface-with-TANG-PRIMER-FPGA Public

    Interfacing Tang primer with VGA display.

    Verilog 8

  6. 8-Bit-ALU-implementation-on-CYCLONE-2 8-Bit-ALU-implementation-on-CYCLONE-2 Public

    Verilog code for 8 Bit ALU and implemented on Intel's Cyclone II

    Verilog