OpenPiton Polara FPGA with plic #4
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hossein1387
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Aug 2, 2024
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| // input mc_clk , | ||
| // input mc_rstn , | ||
| output logic chip_rstn , | ||
| input logic chipset_clk , | ||
| input logic chipset_rstn , | ||
| output logic c0_init_calib_complete, | ||
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| input logic [`NOC_DATA_WIDTH-1:0] mem_flit_in_data , | ||
| input logic mem_flit_in_val , | ||
| output logic mem_flit_in_rdy , |
| logic fifo_trans_rdy; | ||
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| logic [`AXI4_ID_WIDTH -1:0] m_axi_awid; | ||
| logic [`AXI4_ADDR_WIDTH -1:0] m_axi_awaddr; |
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| logic m_axi_awready; | ||
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| logic [`AXI4_ID_WIDTH -1:0] m_axi_wid; |
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The code formatting seems to be not consistent. Please review and remove extra space/tab and comments in the rest of this PR.
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This PR adds support for FPGA emulation of Polara. More specifically it adds the following:
Adding ALVEO U280 board as a target for FPGA implementation of Polara.
Adds timing and implementation constraint for Vivado synthesis.
Logic to instantiate top-level FPGA module for Openpiton framework.
Scripts for automating synthesis and implementation using Vivado in Openpiton framework.