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Merge pull request #2113 from ThalesSiliconSecurity/dev/cvxif
CVXIF : Integrate cvxif tests into CI
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,61 @@ | ||
| /* | ||
| * Copyright 2018 Google LLC | ||
| * Copyright 2020 OpenHW Group | ||
| * Copyright 2023 Thales | ||
| * | ||
| * Licensed under the Apache License, Version 2.0 (the "License"); | ||
| * you may not use this file except in compliance with the License. | ||
| * You may obtain a copy of the License at | ||
| * | ||
| * http://www.apache.org/licenses/LICENSE-2.0 | ||
| * | ||
| * Unless required by applicable law or agreed to in writing, software | ||
| * distributed under the License is distributed on an "AS IS" BASIS, | ||
| * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | ||
| * See the License for the specific language governing permissions and | ||
| * limitations under the License. | ||
| */ | ||
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| //------------------------------------------------------------------------------ | ||
| // CORE-V instruction generator base test: | ||
| // - extension of the RISC-V instruction generator base test. | ||
| // | ||
| //------------------------------------------------------------------------------ | ||
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| class cva6_instr_hazard_test_c extends riscv_instr_base_test; | ||
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| `uvm_component_utils(cva6_instr_hazard_test_c) | ||
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| function new(string name="", uvm_component parent=null); | ||
| super.new(name, parent); | ||
| endfunction | ||
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| virtual function void build_phase(uvm_phase phase); | ||
| override_asm_program_gen(); | ||
| override_gen_config(); | ||
| override_rand_stream(); | ||
| super.build_phase(phase); | ||
| endfunction | ||
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| virtual function void override_asm_program_gen(); | ||
| `uvm_info("CVA6_DV", $sformatf("Overriding ..."), UVM_LOW) | ||
| uvm_factory::get().set_type_override_by_type(riscv_asm_program_gen::get_type(), | ||
| cva6_asm_program_gen_c::get_type()); | ||
| `uvm_info("CVA6_DV", $sformatf("Overrid done "), UVM_LOW) | ||
| endfunction | ||
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| virtual function void override_gen_config(); | ||
| `uvm_info("CVA6_DV", $sformatf("Overriding ..."), UVM_LOW) | ||
| uvm_factory::get().set_type_override_by_type(riscv_instr_gen_config::get_type(), | ||
| cva6_instr_gen_config_c::get_type()); | ||
| `uvm_info("CVA6_DV", $sformatf("Overrid done "), UVM_LOW) | ||
| endfunction | ||
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| virtual function void override_rand_stream(); | ||
| `uvm_info("CVA6_DV", $sformatf("Overriding ..."), UVM_LOW) | ||
| uvm_factory::get().set_type_override_by_type(riscv_rand_instr_stream::get_type(), | ||
| cva6_reg_hazard_stream_c::get_type()); | ||
| `uvm_info("CVA6_DV", $sformatf("Overrid done "), UVM_LOW) | ||
| endfunction | ||
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| endclass : cva6_instr_hazard_test_c |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,62 @@ | ||
| // class for hazard instruction stream (RAW) | ||
| // that means destination register of previous instruction is the same source register of the current instruction | ||
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| class cva6_reg_hazard_stream_c extends riscv_rand_instr_stream; | ||
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| `uvm_object_utils(cva6_reg_hazard_stream_c) | ||
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| string label; | ||
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| function new(string name = ""); | ||
| super.new(name); | ||
| endfunction | ||
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| virtual function void gen_instr(bit no_branch = 1'b0, bit no_load_store = 1'b1, | ||
| bit is_debug_program = 1'b0); | ||
| riscv_reg_t prev_reg; | ||
| cva6_instr_gen_config_c cfg_cva6; | ||
| `DV_CHECK_FATAL($cast(cfg_cva6, cfg), "Could not cast cfg into cfg_cva6") | ||
| setup_allowed_instr(no_branch, no_load_store); | ||
| foreach(instr_list[i]) begin | ||
| if (i == 0) begin | ||
| randomize_instr(instr_list[i], is_debug_program); | ||
| prev_reg = instr_list[i].rd; | ||
| end | ||
| else if (i >= 1) begin | ||
| randomize_instr(instr_list[i], is_debug_program); | ||
| if (!instr_list[i].is_compressed) begin | ||
| `DV_CHECK_RANDOMIZE_WITH_FATAL(instr_list[i], | ||
| if (has_rs1 && cfg_cva6.enable_rdrs1_hazard) { | ||
| instr_list[i].rs1 == prev_reg; | ||
| } | ||
| if (has_rs2 && cfg_cva6.enable_rdrs2_hazard) { | ||
| instr_list[i].rs2 == prev_reg; | ||
| } | ||
| if (cfg_cva6.enable_same_reg) { | ||
| instr_list[i].rd == instr_list[i].rs1; | ||
| instr_list[i].rs1 == instr_list[i].rs2; | ||
| }) | ||
| prev_reg = instr_list[i].rd; | ||
| end | ||
| else begin | ||
| `DV_CHECK_RANDOMIZE_WITH_FATAL(instr_list[i], | ||
| if (instr_list[i-1].rd inside {[S0:A5]}) { | ||
| if (has_rs1 && cfg_cva6.enable_rdrs1_hazard) { | ||
| instr_list[i].rs1 == prev_reg; | ||
| } | ||
| if (has_rs2 && cfg_cva6.enable_rdrs2_hazard) { | ||
| instr_list[i].rs2 == prev_reg; | ||
| }}) | ||
| prev_reg = instr_list[i].rd; | ||
| end | ||
| end | ||
| end | ||
| // Do not allow branch instruction as the last instruction because there's no | ||
| // forward branch target | ||
| while (instr_list[$].category == BRANCH) begin | ||
| void'(instr_list.pop_back()); | ||
| if (instr_list.size() == 0) break; | ||
| end | ||
| endfunction | ||
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| endclass |
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