Fix zfinx_reserved_gpr constraint

Signed-off-by: dd-baoshan <[email protected]>
openhwgroup · Jun 19, 2024 · 4b53f31 · 4b53f31
1 parent 4bc5cfa
commit 4b53f31
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Showing 2 changed files with 2 additions and 2 deletions.
diff --git a/cv32e40p/env/corev-dv/cv32e40p_asm_program_gen.sv b/cv32e40p/env/corev-dv/cv32e40p_asm_program_gen.sv
@@ -430,7 +430,7 @@ class cv32e40p_asm_program_gen extends corev_asm_program_gen;
     //gprs for floating point instructions
     if(RV32ZFINX inside {supported_isa}) begin
       foreach(corev_cfg.zfinx_reserved_gpr[i]) begin
-        if (corev_cfg.zfinx_reserved_gpr[i] inside {ZERO, RA, SP, GP, TP}) continue;
+        if (corev_cfg.zfinx_reserved_gpr[i] inside {ZERO, corev_cfg.ra, corev_cfg.sp, GP, corev_cfg.tp}) continue;
         imm = get_rand_spf_value();
         reg_name = corev_cfg.zfinx_reserved_gpr[i].name();
         str = $sformatf("%0sli%0s %0s, 0x%0x", indent, indent, reg_name.tolower(), imm);

diff --git a/cv32e40p/env/corev-dv/cv32e40p_instr_gen_config.sv b/cv32e40p/env/corev-dv/cv32e40p_instr_gen_config.sv
@@ -158,7 +158,7 @@ class cv32e40p_instr_gen_config extends riscv_instr_gen_config;
       zfinx_reserved_gpr.size() == num_zfinx_reserved_reg;
       unique {zfinx_reserved_gpr};
       foreach(zfinx_reserved_gpr[i]) {
-        !(zfinx_reserved_gpr[i] inside {ZERO, RA, SP, GP, TP, S0, S1, A0, A1, A2, A3, A4, A5});
+        !(zfinx_reserved_gpr[i] inside {ZERO, ra, sp, GP, tp, S0, S1, A0, A1, A2, A3, A4, A5});
         (zfinx_reserved_gpr[i] != dp);
         (zfinx_reserved_gpr[i] != str_rs1);
         (zfinx_reserved_gpr[i] != str_rs3);