make pma 2 clic config, clock sequences, remove todos, add and remove…

… comments Signed-off-by: Kristine Dosvik <[email protected]>
openhwgroup · Dec 17, 2023 · 5c26c21 · 5c26c21
1 parent afbbe5e
commit 5c26c21
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Showing 10 changed files with 219 additions and 18 deletions.
diff --git a/cv32e40s/regress/cv32e40s_full.yaml b/cv32e40s/regress/cv32e40s_full.yaml
@@ -54,6 +54,11 @@ builds:
     cfg: pma_test_cfg_2
     dir: cv32e40s/sim/uvmt
 
+  uvmt_cv32e40s_pma_2_clic:
+    cmd: make comp_corev-dv comp
+    cfg: pma_test_cfg_2_clic
+    dir: cv32e40s/sim/uvmt
+
   uvmt_cv32e40s_pma_3:
     cmd: make comp_corev-dv comp
     cfg: pma_test_cfg_3
@@ -585,7 +590,7 @@ tests:
 
   minhv_pma_block:
     description: test minhv=1 and pma block of mepc address
-    builds: [ uvmt_cv32e40s_pma_2 ]
+    builds: [ uvmt_cv32e40s_pma_2_clic ]
     dir: cv32e40s/sim/uvmt
     cmd: make test TEST=minhv_pma_block
 
diff --git a/cv32e40s/tb/uvmt/support_logic/uvmt_cv32e40s_sl_trigger_match.sv b/cv32e40s/tb/uvmt/support_logic/uvmt_cv32e40s_sl_trigger_match.sv
@@ -76,11 +76,11 @@ module uvmt_cv32e40s_sl_trigger_match
         (rvfi.is_umode && in_support_if.tdata1_array[t][TDATA1_ET_U_MODE]));
 
 
-        // Trigger match instruction:
+      // Trigger match instruction:
       assign trigger_match_execute[t] = csr_conditions_m2_m6[t]
         && in_support_if.tdata1_array[t][TDATA1_EXECUTE]
         && system_conditions
-        && !rvfi.rvfi_trap.clicptr //TODO: KD: burde finne ut hvorfor clicptr er et unntak.
+        && !rvfi.rvfi_trap.clicptr
         && (((rvfi.rvfi_pc_rdata == in_support_if.tdata2_array[t]) && in_support_if.tdata1_array[t][TDATA1_MSB_MATCH:TDATA1_LSB_MATCH] == TDATA1_MATCH_WHEN_EQUAL)
         || ((rvfi.rvfi_pc_rdata >= in_support_if.tdata2_array[t]) && in_support_if.tdata1_array[t][TDATA1_MSB_MATCH:TDATA1_LSB_MATCH] == TDATA1_MATCH_WHEN_GREATER_OR_EQUAL)
         || ((rvfi.rvfi_pc_rdata < in_support_if.tdata2_array[t]) && in_support_if.tdata1_array[t][TDATA1_MSB_MATCH:TDATA1_LSB_MATCH] == TDATA1_MATCH_WHEN_LESSER));

diff --git a/cv32e40s/tb/uvmt/uvmt_cv32e40s_triggers_assert_cov.sv b/cv32e40s/tb/uvmt/uvmt_cv32e40s_triggers_assert_cov.sv
@@ -202,28 +202,33 @@ module uvmt_cv32e40s_triggers_assert_cov
   /////////// Sequences ///////////
 
   sequence seq_csr_read_mmode(csr_addr);
+    @(posedge clknrst_if.clk)
     valid_instr_in_mmode
     && rvfi_if.is_csr_read(csr_addr)
     && rvfi_if.rvfi_rd1_addr != 0;
   endsequence
 
   sequence seq_csr_write_mmode(csr_addr);
+    @(posedge clknrst_if.clk)
     valid_instr_in_mmode
     && rvfi_if.is_csr_write(csr_addr);
   endsequence
 
   sequence seq_csr_read_dmode(csr_addr);
+    @(posedge clknrst_if.clk)
     valid_instr_in_dmode
     && rvfi_if.is_csr_read(csr_addr)
     && rvfi_if.rvfi_rd1_addr != 0;
   endsequence
 
   sequence seq_csr_write_dmode(csr_addr);
+    @(posedge clknrst_if.clk)
     valid_instr_in_dmode
     && rvfi_if.is_csr_write(csr_addr);
   endsequence
 
   sequence seq_tdata1_m2_m6_or_disabled(t);
+    @(posedge clknrst_if.clk)
     valid_instr_in_dmode
     && tselect_pre_state == t
     && (tdata1_pre_state[MSB_TYPE:LSB_TYPE] == TTYPE_MCONTROL
@@ -232,6 +237,7 @@ module uvmt_cv32e40s_triggers_assert_cov
   endsequence
 
   sequence seq_etrigger_hit(t, priv_lvl, exception);
+    @(posedge clknrst_if.clk)
     support_if.trigger_match_exception[t]
     && !rvfi_if.rvfi_dbg_mode
     && priv_lvl
@@ -309,7 +315,7 @@ module uvmt_cv32e40s_triggers_assert_cov
 
   /////////// Assertions and Coverages ///////////
 
-  //Verify that it isonly possible to do 13 Memory transactions:
+  //Verify that it is only possible to do 13 Memory transactions:
   //TODO XIF: this might not be the case for xif, as it can potentionally do more:
 
   a_dt_max_memory_transaction: assert property (
@@ -453,9 +459,9 @@ module uvmt_cv32e40s_triggers_assert_cov
 
     //4)
     a_dt_tselect_higher_than_dbg_num_triggers: assert property(
-      rvfi_if.is_csr_instr(ADDR_TSELECT)
+      rvfi_if.rvfi_valid
       |->
-      rvfi_if.rvfi_rd1_wdata < CORE_PARAM_DBG_NUM_TRIGGERS
+      tselect_post_state < CORE_PARAM_DBG_NUM_TRIGGERS
     ) else `uvm_error(info_tag, "The CSR tselect is set to equal or higher than the number of trigger.\n");
 
 
@@ -946,6 +952,7 @@ module uvmt_cv32e40s_triggers_assert_cov
       && rvfi_if.rvfi_dbg_mode
       && dcsr_if.rvfi_csr_wmask
       |->
+      //If DCSR is written (wmask != 0) there must have been a csr write operation, and not due to a sideeffect of a trigger match
       rvfi_if.is_csr_write(ADDR_DCSR)
     ) else `uvm_error(info_tag, "Action is taken when there is a trigger match while in debug mode (dcsr is changed even though we dont do a dcsr write operation).\n");
 
@@ -954,6 +961,7 @@ module uvmt_cv32e40s_triggers_assert_cov
       && rvfi_if.rvfi_dbg_mode
       && dpc_if.rvfi_csr_wmask
       |->
+      //If DPC is written (wmask != 0) there must have been a csr write operation, and not due to a sideeffect of a trigger match
       rvfi_if.is_csr_write(ADDR_DPC)
     ) else `uvm_error(info_tag, "Action is taken when there is a trigger match while in debug mode (dpc is changed even though we dont do a dpc write operation).\n");
 

diff --git a/...uvmt/uvmt_cv32e40s_xsecure_assert/uvmt_cv32e40s_xsecure_data_independent_timing_assert.sv b/...uvmt/uvmt_cv32e40s_xsecure_assert/uvmt_cv32e40s_xsecure_data_independent_timing_assert.sv
@@ -76,7 +76,7 @@ module uvmt_cv32e40s_xsecure_data_independent_timing_assert
     //There is therefor only 1 empty cycle after a branch instruction.
 
   sequence seq_no_mem_instr_for_cycles(x);
-    (!rvfi_if.is_mem_act)[*x];
+    @(posedge clk_i) (!rvfi_if.is_mem_act)[*x];
   endsequence
 
   a_xsecure_dataindtiming_branch_timing_pc_hardening_disabled: assert property (
@@ -114,7 +114,7 @@ module uvmt_cv32e40s_xsecure_data_independent_timing_assert
   //Verify that execution of division or (division)-remainder have non-varying timing when the data independent timing feature is enabled
 
   sequence seq_no_rvalid_for_past_34_cycles;
-    (!rvfi_if.rvfi_valid[*34] ##1 1);
+    @(posedge clk_i) (!rvfi_if.rvfi_valid[*34] ##1 1);
   endsequence
 
   a_xsecure_dataindtiming_div_rem_timing: assert property (

diff --git a/cv32e40s/tb/uvmt/uvmt_cv32e40s_xsecure_assert/uvmt_cv32e40s_xsecure_dummy_and_hint_assert.sv b/cv32e40s/tb/uvmt/uvmt_cv32e40s_xsecure_assert/uvmt_cv32e40s_xsecure_dummy_and_hint_assert.sv
@@ -702,6 +702,7 @@ module uvmt_cv32e40s_xsecure_dummy_and_hint_assert
   //Verify that the LFSR's seeds are reset when lockups are detected
 
   sequence seq_xsecure_dummy_hint_instr_LFSRx_lockup_detection(logic get_new_lfsr_value, logic seed_we, logic [31:0] seed_w_value, logic [31:0] lfsr_n);
+    @(posedge clk_i)
 
     (rnddummy_enabled || rndhint_enabled)
     && get_new_lfsr_value

diff --git a/cv32e40s/tb/uvmt/uvmt_cv32e40s_xsecure_assert/uvmt_cv32e40s_xsecure_hardened_pc_assert.sv b/cv32e40s/tb/uvmt/uvmt_cv32e40s_xsecure_assert/uvmt_cv32e40s_xsecure_hardened_pc_assert.sv
@@ -195,6 +195,7 @@ module uvmt_cv32e40s_xsecure_hardened_pc_assert
   //Verify that the major alert is set due to pc hardening fault when the PC target of a jump instruction or a branch decision is unstable, and the PC hardening feature is enabled
 
   sequence seq_non_hardened_jump(kill, halt, instr, first_op, jump_addr);
+    @(posedge clk_i)
 
     (!kill && !halt) throughout
 

diff --git a/.../tb/uvmt/uvmt_cv32e40s_xsecure_assert/uvmt_cv32e40s_xsecure_interface_integrity_assert.sv b/.../tb/uvmt/uvmt_cv32e40s_xsecure_assert/uvmt_cv32e40s_xsecure_interface_integrity_assert.sv
@@ -369,6 +369,7 @@ module uvmt_cv32e40s_xsecure_interface_integrity_assert
   //But only if integrity checking is enabled
 
   sequence seq_checksum_fault(rvalid, req_had_integrity, memory_op, rchk_input, rchk_calculated);
+    @(posedge clk_i)
     rvalid
     && req_had_integrity
     && memory_op

diff --git a/cv32e40s/tests/cfg/pma_test_cfg_2.yaml b/cv32e40s/tests/cfg/pma_test_cfg_2.yaml
@@ -2,10 +2,8 @@ name: pma_test_cfg_2
 description: PMA configuration for the PMA_TEST_CFG_2 test case
 compile_flags: >
    +define+PMA_TEST_CFG_2
-   +define+CLIC_EN
    +define+ZBA_ZBB_ZBC_ZBS
 plusargs: >
-   +enable_clic=1
    +enable_pma=1
    +enable_zca_extension=1
    +enable_zcb_extension=1
@@ -18,13 +16,6 @@ plusargs: >
    +enable_zbc_extension=1
    +enable_zbs_extension=1
 ovpsim: >
-   --override cpu/CLICLEVELS=256
-   --override cpu/CLICXCSW=T
-   --override cpu/CLICXNXTI=T
-   --override cpu/CLICSELHVEC=T
-   --override cpu/CLICINTCTLBITS=8
-   --override cpu/CLIC_version=master
-   --override cpu/externalCLIC=T
    --override cpu/PMP_registers=64
    --override cpu/PMP_undefined=T
    --override cpu/PMP_initialparams=T

diff --git a/cv32e40s/tests/cfg/pma_test_cfg_2_clic.yaml b/cv32e40s/tests/cfg/pma_test_cfg_2_clic.yaml
@@ -0,0 +1,194 @@
+name: pma_test_cfg_2
+description: PMA configuration for the PMA_TEST_CFG_2 test case
+compile_flags: >
+   +define+PMA_TEST_CFG_2
+   +define+CLIC_EN
+   +define+ZBA_ZBB_ZBC_ZBS
+plusargs: >
+   +enable_clic=1
+   +enable_pma=1
+   +enable_zca_extension=1
+   +enable_zcb_extension=1
+   +enable_zcmt_extension=1
+   +enable_zcmp_extension=1
+   +fix_ra=1
+   +fix_sp=1
+   +enable_zba_extension=1
+   +enable_zbb_extension=1
+   +enable_zbc_extension=1
+   +enable_zbs_extension=1
+ovpsim: >
+   --override cpu/CLICLEVELS=256
+   --override cpu/CLICXCSW=T
+   --override cpu/CLICXNXTI=T
+   --override cpu/CLICSELHVEC=T
+   --override cpu/CLICINTCTLBITS=8
+   --override cpu/CLIC_version=master
+   --override cpu/externalCLIC=T
+   --override cpu/PMP_registers=64
+   --override cpu/PMP_undefined=T
+   --override cpu/PMP_initialparams=T
+   --override cpu/PMP_maskparams=T
+   --override cpu/pmpaddr0=0
+   --override cpu/pmpaddr1=0
+   --override cpu/pmpaddr2=0
+   --override cpu/pmpaddr3=0
+   --override cpu/pmpaddr4=0
+   --override cpu/pmpaddr5=0
+   --override cpu/pmpaddr6=0
+   --override cpu/pmpaddr7=0
+   --override cpu/pmpaddr8=0
+   --override cpu/pmpaddr9=0
+   --override cpu/pmpaddr10=0
+   --override cpu/pmpaddr11=0
+   --override cpu/pmpaddr12=0
+   --override cpu/pmpaddr13=0
+   --override cpu/pmpaddr14=0
+   --override cpu/pmpaddr15=0
+   --override cpu/pmpaddr16=0
+   --override cpu/pmpaddr17=0
+   --override cpu/pmpaddr18=0
+   --override cpu/pmpaddr19=0
+   --override cpu/pmpaddr20=0
+   --override cpu/pmpaddr21=0
+   --override cpu/pmpaddr22=0
+   --override cpu/pmpaddr23=0
+   --override cpu/pmpaddr24=0
+   --override cpu/pmpaddr25=0
+   --override cpu/pmpaddr26=0
+   --override cpu/pmpaddr27=0
+   --override cpu/pmpaddr28=0
+   --override cpu/pmpaddr29=0
+   --override cpu/pmpaddr30=0
+   --override cpu/pmpaddr31=0
+   --override cpu/pmpaddr32=0
+   --override cpu/pmpaddr33=0
+   --override cpu/pmpaddr34=0
+   --override cpu/pmpaddr35=0
+   --override cpu/pmpaddr36=0
+   --override cpu/pmpaddr37=0
+   --override cpu/pmpaddr38=0
+   --override cpu/pmpaddr39=0
+   --override cpu/pmpaddr40=0
+   --override cpu/pmpaddr41=0
+   --override cpu/pmpaddr42=0
+   --override cpu/pmpaddr43=0
+   --override cpu/pmpaddr44=0
+   --override cpu/pmpaddr45=0
+   --override cpu/pmpaddr46=0
+   --override cpu/pmpaddr47=0
+   --override cpu/pmpaddr48=0
+   --override cpu/pmpaddr49=0
+   --override cpu/pmpaddr50=0
+   --override cpu/pmpaddr51=0
+   --override cpu/pmpaddr52=0
+   --override cpu/pmpaddr53=0
+   --override cpu/pmpaddr54=0
+   --override cpu/pmpaddr55=0
+   --override cpu/pmpaddr56=0
+   --override cpu/pmpaddr57=0
+   --override cpu/pmpaddr58=0
+   --override cpu/pmpaddr59=0
+   --override cpu/pmpaddr60=0
+   --override cpu/pmpaddr61=0
+   --override cpu/pmpaddr62=0
+   --override cpu/pmpaddr63=0
+   --override cpu/pmpcfg0=0
+   --override cpu/pmpcfg1=0
+   --override cpu/pmpcfg2=0
+   --override cpu/pmpcfg3=0
+   --override cpu/pmpcfg4=0
+   --override cpu/pmpcfg5=0
+   --override cpu/pmpcfg6=0
+   --override cpu/pmpcfg7=0
+   --override cpu/pmpcfg8=0
+   --override cpu/pmpcfg9=0
+   --override cpu/pmpcfg10=0
+   --override cpu/pmpcfg11=0
+   --override cpu/pmpcfg12=0
+   --override cpu/pmpcfg13=0
+   --override cpu/pmpcfg14=0
+   --override cpu/pmpcfg15=0
+   --override cpu/mask_pmpaddr0=0x00000000
+   --override cpu/mask_pmpaddr1=0x00000000
+   --override cpu/mask_pmpaddr2=0x00000000
+   --override cpu/mask_pmpaddr3=0x00000000
+   --override cpu/mask_pmpaddr4=0x00000000
+   --override cpu/mask_pmpaddr5=0x00000000
+   --override cpu/mask_pmpaddr6=0x00000000
+   --override cpu/mask_pmpaddr7=0x00000000
+   --override cpu/mask_pmpaddr8=0x00000000
+   --override cpu/mask_pmpaddr9=0x00000000
+   --override cpu/mask_pmpaddr10=0x00000000
+   --override cpu/mask_pmpaddr11=0x00000000
+   --override cpu/mask_pmpaddr12=0x00000000
+   --override cpu/mask_pmpaddr13=0x00000000
+   --override cpu/mask_pmpaddr14=0x00000000
+   --override cpu/mask_pmpaddr15=0x00000000
+   --override cpu/mask_pmpaddr16=0x00000000
+   --override cpu/mask_pmpaddr17=0x00000000
+   --override cpu/mask_pmpaddr18=0x00000000
+   --override cpu/mask_pmpaddr19=0x00000000
+   --override cpu/mask_pmpaddr20=0x00000000
+   --override cpu/mask_pmpaddr21=0x00000000
+   --override cpu/mask_pmpaddr22=0x00000000
+   --override cpu/mask_pmpaddr23=0x00000000
+   --override cpu/mask_pmpaddr24=0x00000000
+   --override cpu/mask_pmpaddr25=0x00000000
+   --override cpu/mask_pmpaddr26=0x00000000
+   --override cpu/mask_pmpaddr27=0x00000000
+   --override cpu/mask_pmpaddr28=0x00000000
+   --override cpu/mask_pmpaddr29=0x00000000
+   --override cpu/mask_pmpaddr30=0x00000000
+   --override cpu/mask_pmpaddr31=0x00000000
+   --override cpu/mask_pmpaddr32=0x00000000
+   --override cpu/mask_pmpaddr33=0x00000000
+   --override cpu/mask_pmpaddr34=0x00000000
+   --override cpu/mask_pmpaddr35=0x00000000
+   --override cpu/mask_pmpaddr36=0x00000000
+   --override cpu/mask_pmpaddr37=0x00000000
+   --override cpu/mask_pmpaddr38=0x00000000
+   --override cpu/mask_pmpaddr39=0x00000000
+   --override cpu/mask_pmpaddr40=0x00000000
+   --override cpu/mask_pmpaddr41=0x00000000
+   --override cpu/mask_pmpaddr42=0x00000000
+   --override cpu/mask_pmpaddr43=0x00000000
+   --override cpu/mask_pmpaddr44=0x00000000
+   --override cpu/mask_pmpaddr45=0x00000000
+   --override cpu/mask_pmpaddr46=0x00000000
+   --override cpu/mask_pmpaddr47=0x00000000
+   --override cpu/mask_pmpaddr48=0x00000000
+   --override cpu/mask_pmpaddr49=0x00000000
+   --override cpu/mask_pmpaddr50=0x00000000
+   --override cpu/mask_pmpaddr51=0x00000000
+   --override cpu/mask_pmpaddr52=0x00000000
+   --override cpu/mask_pmpaddr53=0x00000000
+   --override cpu/mask_pmpaddr54=0x00000000
+   --override cpu/mask_pmpaddr55=0x00000000
+   --override cpu/mask_pmpaddr56=0x00000000
+   --override cpu/mask_pmpaddr57=0x00000000
+   --override cpu/mask_pmpaddr58=0x00000000
+   --override cpu/mask_pmpaddr59=0x00000000
+   --override cpu/mask_pmpaddr60=0x00000000
+   --override cpu/mask_pmpaddr61=0x00000000
+   --override cpu/mask_pmpaddr62=0x00000000
+   --override cpu/mask_pmpaddr63=0x00000000
+   --override cpu/mask_pmpcfg0=0x00000000
+   --override cpu/mask_pmpcfg1=0x00000000
+   --override cpu/mask_pmpcfg2=0x00000000
+   --override cpu/mask_pmpcfg3=0x00000000
+   --override cpu/mask_pmpcfg4=0x00000000
+   --override cpu/mask_pmpcfg5=0x00000000
+   --override cpu/mask_pmpcfg6=0x00000000
+   --override cpu/mask_pmpcfg7=0x00000000
+   --override cpu/mask_pmpcfg8=0x00000000
+   --override cpu/mask_pmpcfg9=0x00000000
+   --override cpu/mask_pmpcfg10=0x00000000
+   --override cpu/mask_pmpcfg11=0x00000000
+   --override cpu/mask_pmpcfg12=0x00000000
+   --override cpu/mask_pmpcfg13=0x00000000
+   --override cpu/mask_pmpcfg14=0x00000000
+   --override cpu/mask_pmpcfg15=0x00000000
+cflags: >
+    -Wl,--nmagic
+cv_sw_march: rv32im_zba1p00_zbb1p00_zbc1p00_zbs1p00_zicsr_zca_zcb_zcmp_zcmt_zifencei
diff --git a/cv32e40s/tests/programs/custom/mhpmcounter_write_test/test.yaml b/cv32e40s/tests/programs/custom/mhpmcounter_write_test/test.yaml
@@ -1,4 +1,4 @@
 name: mhpmcounter_write_test
 uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c
 description: >
-    Write to mhpmcounters. Is only verifyed by ISS, should be verifyed that we get excpected behaviour?
+    Write to the mhpmcounters.