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verible
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Signed-off-by: Pascal Gouedo <[email protected]>
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Pascal Gouedo committed Mar 25, 2024
1 parent 7a843ea commit 3bbcbe9
Showing 1 changed file with 2 additions and 2 deletions.
4 changes: 2 additions & 2 deletions rtl/cv32e40p_id_stage.sv
Original file line number Diff line number Diff line change
Expand Up @@ -1514,8 +1514,8 @@ module cv32e40p_id_stage
if (id_valid_o) begin // unstall the whole pipeline
alu_en_ex_o <= alu_en;
if (alu_en) begin
alu_operator_ex_o <= alu_operator;
alu_operand_a_ex_o <= alu_operand_a;
alu_operator_ex_o <= alu_operator;
alu_operand_a_ex_o <= alu_operand_a;
if (alu_op_b_mux_sel == OP_B_REGB_OR_FWD && (alu_operator == ALU_CLIP || alu_operator == ALU_CLIPU)) begin
alu_operand_b_ex_o <= {1'b0, alu_operand_b[30:0]};
end else begin
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